Patent classifications
B81C1/00373
Patterned structure for electronic device and manufacturing method thereof
The present invention provides a patterned structure for an electronic device and a manufacturing method thereof. The patterned structure includes a patterned layer, a blocking structure, a cantilever structure, and a connection structure. The patterned layer is disposed on a substrate. The blocking structure is disposed on the substrate at one side of the patterned layer, wherein a thickness of the blocking structure is smaller than a thickness of the patterned layer. The cantilever structure is disposed on the substrate and located between the patterned layer and the blocking structure. The cantilever structure is connected with the patterned layer and the blocking structure. The connection structure is connected between the patterned layer and the substrate at one side of the patterned layer, and located on the cantilever structure and the blocking structure.
Liquid guiding boundaries for porous substrates providing increased biodegradability
The present invention relates to a method for manufacturing structural layers for guiding liquid flow on a porous substrate, by printing onto at least one area of at least one surface of the substrate a printing solution containing an aqueous dispersion of a poly(lactic acid)-based copolymer.
Additive Manufacturing Methods for Modification and Improvement of the Surfaces of Micro-Scale Geometric Features
The present disclosure addresses methods to refine the geometry of micro features manufactured in various substrates. Such refinement includes improvement in edge roughness and roughness of aperture channel walls. The methods include deposition of material onto feature edges and surfaces as well as placement of micro fabricated inserts into coarse features. Foremost among the candidate technologies that can be employed for these purposes are two photon polymerization-based 3D nano printing and atomic force microscope nanopipette-based electroplating.
Printing transferable components using microstructured elastomeric surfaces with pressure modulated reversible adhesion
In a method of printing a transferable component, a stamp including an elastomeric post having three-dimensional relief features protruding from a surface thereof is pressed against a component on a donor substrate with a first pressure that is sufficient to mechanically deform the relief features and a region of the post between the relief features to contact the component over a first contact area. The stamp is retracted from the donor substrate such that the component is adhered to the stamp. The stamp including the component adhered thereto is pressed against a receiving substrate with a second pressure that is less than the first pressure to contact the component over a second contact area that is smaller than the first contact area. The stamp is then retracted from the receiving substrate to delaminate the component from the stamp and print the component onto the receiving substrate. Related apparatus and stamps are also discussed.
Precision alignment of the substrate coordinate system relative to the inkjet coordinate system
A method and alignment system for minimizing errors in the deposition of films of tailored thickness. A first position on a stage is identified for optimal placement of a downward looking microscope (DLM) and an upward looking microscope (ULM) when alignment marks on the DLM and ULM are aligned, where the DLM is attached to a bridge and the ULM is attached to the stage. A second position on the stage is identified when the ULM on the stage is aligned with the alignment marks on a metrology tool. A surface of a chucked substrate affixed to the stage is then measured. A map between a substrate coordinate system and a metrology coordinate system may then be obtained using the measured surface of the chucked substrate with the first and second positions.
Selectively controlling application of a self-assembled monolayer coating on a substrate of a device for facilitating a reduction of adverse effects of such coating on the device
Selectively controlling application of a self-assembled monolayer (SAM) coating on a substrate of a device is presented herein. A method comprises: forming a material on a first substrate; removing a selected portion of the material from a defined contact area of the first substrate; forming a SAM coating on the material and the defined contact areathe SAM coating comprising a first adhesion force with respect to the material and a second adhesion force with respect to the defined contact area, and the first adhesion force being less than the second adhesion force; removing the SAM coating that has been formed on the material; and attaching the first substrate to the second substratethe first substrate being positioned across from the second substrate, and the SAM coating that has been formed on the defined contact area being positioned across from a bump stop of the second substrate.
MICROELECTRONIC DEVICE SUBSTRATE FORMED BY ADDITIVE PROCESS
A microelectronic device is formed by forming at least a portion of a substrate of the microelectronic device by one or more additive processes. The additive processes may be used to form semiconductor material of the substrate. The additive processes may also be used to form dielectric material structures or electrically conductive structures, such as metal structures, of the substrate. The additive processes are used to form structures of the substrate which would be costly or impractical to form using planar processes. In one aspect, the substrate may include multiple doped semiconductor elements, such as wells or buried layers, having different average doping densities, or depths below a component surface of the substrate. In another aspect, the substrate may include dielectric isolation structures with semiconductor material extending at least partway over and under the dielectric isolation structures. Other structures of the substrate are disclosed.
Rubbing-Induced Site-Selective Growth Of Device Patterns
The superior electronic and mechanical properties of 2D-layered transition metal dichalcogenides and other 2D layered materials could be exploited to make a broad range of devices with attractive functionalities. However, the nanofabrication of such layered-material-based devices still needs resist-based lithography and plasma etching processes for patterning layered materials into functional device features. Such patterning processes lead to unavoidable contaminations, to which the transport characteristics of atomically-thin layered materials are very sensitive. More seriously, such lithography-introduced contaminants cannot be safely eliminated by conventional material wafer cleaning approaches. This disclosure introduces a rubbing-induced site-selective growth method capable of directly generating few-layer molybdenum disulfide device patterns without the need of any additional patterning processes. This method consists of two critical steps: (i) a damage-free mechanical rubbing process for generating microscale triboelectric charge patterns on a dielectric surface, and (ii) site-selective deposition of molybdenum disulfide or the like within rubbing-induced charge patterns.
SELECTIVE STEP COVERAGE FOR MICRO-FABRICATED STRUCTURES
A shadow mask having two or more levels of openings enables selective step coverage of micro-fabricated structures within a micro-optical bench device. The shadow mask includes a first opening within a top surface of the shadow mask and a second opening within the bottom surface of the shadow mask. The second opening is aligned with the first opening and has a second width less than a first width of the first opening. An overlap between the first opening and the second opening forms a hole within the shadow mask through which selective coating of micro-fabricated structures within the micro-optical bench device may occur.
ANTI-STICTION PROCESS FOR MEMS DEVICE
A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.