A method of producing an etching mask. A substrate is provided, a metal layer is applied, the metal layer comprises or is formed from at least one transition metal and/or aluminum. A masking layer is applied and the masking layer is structured. The metal layer is exposed in at least one processing region. The substrate is coated with a tetrel layer including at least partially a tetrel, wherein an interdiffusion zone between the transition metal or aluminum and the tetrel is formed in the processing region at an interface between the metal layer and the tetrel layer. The masking layer is removed and the metal layer s selectively etched. The substrate is exposed in at least one etching region other than the processing region, and the metal layer is at least partially maintained in the processing region.

A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed. The present invention can form a plurality of deep trenches with high aspect ratio on the MEMS sealing cap silicon substrate using conventional semiconductor processes, avoiding the problem that the conventional spin coating cannot be conducted on a sealing cap wafer with deep trenches using photoresist.

There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.

A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.

A process for fabricating a symmetrical MEMS accelerometer. A pair of half parts is fabricated by, for each half part: (i) forming a plurality of resilient beams, first connecting parts, second connecting parts, and a plurality of comb structures, by etching a plurality of holes on a bottom surface of a first silicon wafer; (ii) etching a plurality of hollowed parts on a top surface of a second silicon wafer; (iii) forming a silicon dioxide layer on the top and bottom surface of the second silicon wafer; (iv) bonding the bottom surface of the first silicon wafer with the top surface of the second silicon wafer; (v) depositing a layer of silicon nitride on the bottom surface of the second silicon wafer, and removing parts of the silicon nitride layer and silicon dioxide layer on the bottom surface of the second silicon wafer; (vii) deep etching the exposed parts of the bottom surface of the second silicon wafer to the silicon dioxide layer located on the top surface of the second silicon wafer, and reducing the thickness of the first silicon wafer; and (viii) removing the silicon nitride layer, and etching the silicon dioxide to form the mass. The two half parts are then bonded along their bottom surface. The device is deep etched to form a movable accelerometer. A bottom cap is fabricated by hollowing out the corresponding area, and depositing metal as electrodes. The accelerometer is bonded with the bottom cap. Metal is deposited on the first silicon wafer to form electrodes.

Graphoepitaxy directed self-assembly methods generally include grafting a conformal layer of a polymer brush onto a topographic substrate. A planarization material, which functions as a sacrificial material is coated onto the topographic substrate. The planarization material is etched back to a top surface of the topographic substrate, wherein the etch back removes the polymer brush from the top surfaces of the topographic substrate. The remaining portion of the polymer brush is protected by the remaining planarization material below the top surface of the topographic substrate, which can be removed with a solvent to provide the topographic substrate with a conformal polymer brush below the top surface of the topographic substrate. The substrate is then coated with a block copolymer and annealed to direct self-assembly of the block copolymer. The methods mitigate island and/or hole defect formation.

A MEMS device is formed by applying a lower polymer film to top surfaces of a common substrate containing a plurality of MEMS devices, and patterning the lower polymer film to form a headspace wall surrounding components of each MEMS device. Subsequently an upper polymer dry film is applied to top surfaces of the headspace walls and patterned to form headspace caps which isolate the components of each MEMS device. Subsequently, the MEMS devices are singulated to provide separate MEMS devices.

A device and a method for manufacturing it are disclosed wherein the devices comprises a substrate and at least a first layer and a second layer that are partially etched, all made of inorganic materials, and wherein the at least partially etched first layer and the at least partially etched second layer form together a suspended structure, and wherein each of the first layer and the second layer has a different pre-determined shape from the other.

A method of forming at least one lithography feature, the method including: providing at least one lithography recess on a substrate, the or each lithography recess having at least one side-wall and a base, with the at least one side-wall having a width between portions thereof; providing a self-assemblable block copolymer having first and second blocks in the or each lithography recess; causing the self-assemblable block copolymer to self-assemble into an ordered layer within the or each lithography recess, the ordered layer including at least a first domain of first blocks and a second domain of second blocks; causing the self-assemblable block copolymer to cross-link in a directional manner; and selectively removing the first domain to form lithography features of the second domain within the or each lithography recess.