A method of forming a resonator by providing a first layer; forming a sacrificial layer on the first layer; forming a capping layer on the sacrificial layer; forming at least one etching aperture in the capping layer; forming at least one additional aperture having a different size than the at least one etching aperture; forming a cavity and releasing a resonator structure within the cavity by removing the sacrificial layer by etching via the at least one etching aperture; sealing the at least one etching aperture; and forming a lining in the at least one additional aperture.

Graphoepitaxy directed self-assembly methods generally include grafting a conformal layer of a polymer brush onto a topographic substrate. A planarization material, which functions as a sacrificial material is coated onto the topographic substrate. The planarization material is etched back to a top surface of the topographic substrate, wherein the etch back removes the polymer brush from the top surfaces of the topographic substrate. The remaining portion of the polymer brush is protected by the remaining planarization material below the top surface of the topographic substrate, which can be removed with a solvent to provide the topographic substrate with a conformal polymer brush below the top surface of the topographic substrate. The substrate is then coated with a block copolymer and annealed to direct self-assembly of the block copolymer. The methods mitigate island and/or hole defect formation.

A MEMS device is formed by applying a lower polymer film to top surfaces of a common substrate containing a plurality of MEMS devices, and patterning the lower polymer film to form a headspace wall surrounding components of each MEMS device. Subsequently an upper polymer dry film is applied to top surfaces of the headspace walls and patterned to form headspace caps which isolate the components of each MEMS device. Subsequently, the MEMS devices are singulated to provide separate MEMS devices.

In the method, a sidewall pattern is formed in a side wall of a first resist pattern that is formed on a second hard mask layer of a base material in which first and second hard mask layers are laminated in the order of description, a second hard mask pattern is formed by etching the second hard mask layer by using the sidewall pattern as a mask, a first hard mask pattern is formed by etching the first hard mask layer by using, as a mask, the second hard mask pattern and a second resist pattern that is formed on the first hard mask layer of the base material, and the first and second fine patterns are formed by etching the base material by using the first hard mask pattern as a mask.

A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.

In an example, a method includes depositing an organic polymer layer on one or more material layers. The method also includes thermally curing the organic polymer layer. The method includes depositing a hard mask on the organic polymer layer and depositing a photoresist layer on the hard mask. The method also includes patterning the photoresist layer to expose at least a portion of the hard mask. The method includes etching the exposed portion of the hard mask to expose at least a portion of the organic polymer layer. The method also includes etching the exposed portion of the organic polymer layer to expose at least a portion of the one or more material layers.

A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.

There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

A method creates MEMS structures by selectively etching a silicon wafer that is patterned by using a masking layer. The method comprises depositing and patterning a first mask on a silicon wafer to define desired first areas on the wafer to be etched. First trenches are etched on parts of the wafer not covered by the first mask. The first trenches are filled with a deposit layer. A part of the deposit layer is removed on desired second areas to be etched and a remainder is left on areas to function as a second mask to define final structures. Parts of the wafer on the desired second areas is etched, and the second mask is removed. A gyroscope or accelerator can be manufactured by dimensioning the structures.

A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.