A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.

A method includes tab dicing a region of a tab region disposed between a first die and a second die. The tab region structurally connects the first die to the second die each including a MEMS device eutecticly bonded to a CMOS device. The tab region includes a handle wafer layer disposed over a fusion bond oxide layer that is disposed on an ACT layer. The tab region is positioned above a CMOS tab region that with the first and second die form a cavity therein. The tab dicing cuts through the handle wafer layer and leaves a portion of the fusion bond oxide layer underneath the handle wafer layer to form an oxide tether within the tab region. The oxide tether maintains the tab region in place and above the CMOS tab region. Subsequent to the tab dicing the first region, the tab region is removed.

A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.

A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.

A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.

An actuator includes a first driving beam that is connected to an object to be driven and includes multiple first beams extending in a direction orthogonal to a first predetermined axis, ends of each adjacent pair of the first beams being connected to each other via one of first turnaround parts such that the first driving beam forms a zig-zag bellows structure as a whole; first driving sources formed on first surfaces of the first beams; and ribs formed on second surfaces of the first beams at positions that are closer to the first predetermined axis than the first turnaround parts. The first driving sources are configured to move the first driving beam and thereby rotate the object around the first predetermined axis.

A fabrication method includes arranging a plurality of dice on a substrate and performing a first etching process that etches a first layer of the substrate at a boundary between adjacent dice on the substrate. The etching forms facets of one or more waveguides that are defined within the first layer, and the etching leaves a portion of the first layer in the boundary between the adjacent dice. The method continues with a second etching process that etches the portion of the first layer and a second layer beneath the portion of the first layer, the second etching process forming a trench in the boundary where the second layer has a different material than the first layer. The method also includes separating the dice from one another along the trench.

In described examples, a device mounted on a substrate includes an encapsulant. In at least one example, an encapsulant barrier is deposited along a scribe line, along which the substrate is singulatable. To encapsulate one or more terminals of the substrate, an encapsulant is deposited between the encapsulant barrier and an edge of the device parallel to the encapsulant barrier.

A sensor device comprises a sensitive element (1) and a support (2) for the sensitive element, the support having a surface (3) with an access opening (4) to the sensitive element (1). A layer of adhesive material (5) covers at least parts of the surface (3). A venting medium (6) extends over the entire surface (3) of the support (2) and the access opening (4) and is attached to the support (2) by the layer of adhesive material (5).

The invention relates to a method of processing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area having no devices and being formed around the device area, wherein the device area is formed with a plurality of protrusions protruding from a plane surface of the wafer. The method comprises attaching a protective film, for covering the devices on the wafer, to the one side of the wafer, wherein the protective film is adhered to at least a part of the one side of the wafer with an adhesive, and providing a carrier having a curable resin applied to a front surface thereof. The method further comprises attaching the one side of the wafer, having the protective film attached thereto, to the front surface of the carrier, so that the protrusions protruding from the plane surface of the wafer are embedded in the curable resin and a back surface of the carrier opposite to the front surface thereof is substantially parallel to the side of the wafer being opposite to the one side, and grinding the side of the wafer being opposite to the one side for adjusting the wafer thickness.