In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.

A method of manufacturing a MEMS chip includes: providing a silicon substrate layer, the silicon substrate layer comprising a front surface configured to perform a MEMS process and a rear surface opposite to the front surface; growing a first oxidation layer mainly made of SiO.sub.2 on the rear surface of the silicon substrate layer by performing a thermal oxidation process; and depositing a first thin film layer mainly made of silicon nitride on the first oxidation layer by performing a low pressure chemical vapor deposition process.

Integrated MEMS-CMOS devices and integrated circuits with MEMS devices and CMOS devices are provided. An exemplary integrated MEMS-CMOS device is vertically integrated and includes a substrate having a first side and a second side opposite the first side. Further, the exemplary vertically integrated MEMS-CMOS device includes a CMOS device located in and/or over the first side of the substrate. Also, the exemplary vertically integrated MEMS-CMOS device includes a MEMS device located in and/or under the second side of the substrate.

Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate and a MEMS substrate bonded with the CMOS substrate. The CMOS substrate includes a semiconductor substrate, a first dielectric layer formed over the semiconductor substrate, and a plurality of conductive pads formed in the first dielectric layer. The MEMS substrate includes a semiconductor layer having a movable element and a second dielectric layer formed between the semiconductor layer and the CMOS substrate. The MEMS substrate also includes a closed chamber surrounding the movable element. The MEMS substrate further includes a blocking layer formed between the closed chamber and the first dielectric layer of the CMOS substrate. The blocking layer is configured to block gas, coming from the first dielectric layer, from entering the closed chamber.

A microelectronic component arrangement includes a sensor and a carrier. The sensor has a detection surface and a region including contact elements situated at a first distance with respect to one another. The carrier includes a mounting surface, and the sensor is fixed on the carrier by the contact elements situated at a first distance with respect to one another at least regionally. The detection surface is opposite the mounting surface in a manner having a second distance with respect to the mounting surface. The contact elements are wetted by a mechanically stabilizing material, the region including the contact elements is enclosed by the mechanically stabilizing material, and the detection surface is free of the mechanically stabilizing material.

A manufacturing method of an electronic device includes a process that forms a protective layer on at least a portion of the first base body to which a third base body is to be bonded, a process that performs first bonding of a second base body to the first base body, a process that performs a first etching of the second base body bonded by the first bonding, a process that removes the protective layer using a second etching, and a process that performs second bonding of the third base body to the first base body. In the first etching, an etching rate of the second base body is faster than those of the first base body and the protective layer, and in the second etching, an etching rate of the protective layer is faster than those of the first base body and the second base body.

A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

A method of transferring graphene onto a target substrate having cavities and/or holes or onto a substrate having at least one water soluble layer is disclosed. It comprises the steps of: applying a protective layer (4) onto a sample comprising a stack (20) formed by a graphene monolayer (2) grown on a metal foil or on a metal thin film on a silicon substrate (1); attaching to said protective layer (4) a frame (5) comprising at least one outer border and at least one inner border, said frame (5) comprising a substrate and a thermal release adhesive polymer layer, the frame (5) providing integrity and allowing the handling of said sample; removing or detaching said metal foil or metal thin film on a silicon substrate (1); once the metal foil or metal thin film on a silicon substrate (1) has been removed or detached, drying the sample; depositing the sample onto a substrate (7); removing said frame (5) by cutting through said protective layer (4) at said at least one inner border of the frame (5) or by thermal release.

The invention relates to a method of processing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area having no devices and being formed around the device area, wherein the device area is formed with a plurality of protrusions protruding from a plane surface of the wafer. The method comprises attaching a protective film, for covering the devices on the wafer, to the one side of the wafer, wherein the protective film is adhered to at least a part of the one side of the wafer with an adhesive, and providing a carrier having a curable resin applied to a front surface thereof. The method further comprises attaching the one side of the wafer, having the protective film attached thereto, to the front surface of the carrier, so that the protrusions protruding from the plane surface of the wafer are embedded in the curable resin and a back surface of the carrier opposite to the front surface thereof is substantially parallel to the side of the wafer being opposite to the one side, and grinding the side of the wafer being opposite to the one side for adjusting the wafer thickness.

Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.