This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line.

A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

A method for setting a pressure in a cavern formed using a substrate and a substrate cap, the cavern being part of a semiconductor system, including an additional cavern formed with using the substrate and of the substrate cap, a microelectromechanical system being situated in the cavern, an additional microelectromechanical system being situated in the additional cavern, a diffusion area being situated in the substrate and/or in the substrate cap, the method includes a gas diffusing with the aid of the diffusion area from the surroundings into the cavern, during the diffusing, a diffusivity and/or a diffusion flow of the gas from the surroundings into the cavern being greater than an additional diffusivity and/or an additional diffusion flow of the gas from the surroundings into the additional cavern, and/or during the diffusing, the additional cavern being at least essentially protected from a penetration of the gas into the additional cavern.

A sensor package and a method for producing a sensor package are disclosed. In an embodiment a method for producing a sensor package includes providing a carrier including electric conductors, fastening a dummy die or interposer to the carrier, providing an ASIC device including an integrated sensor element and fastening the ASIC device to the dummy die or interposer.

A method includes forming a recess in a first substrate, bonding a micro-electro-mechanical systems (MEMS) substrate to the first substrate after forming the recess in the first substrate, forming an anti-stiction layer over the micro-electro-mechanical systems (MEMS) substrate, pattering the anti-stiction layer, etching the MEMS substrate to form a MEMS device, and bonding the MEMS device and the first substrate to a second substrate. The patterned anti-stiction layer is between the MEMS device and the second substrate.

Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.

A device comprising a micro-electro-mechanical system (MEMS) substrate with protrusions of different heights that has been integrated with a complementary metal-oxide-semiconductor (CMOS) substrate is presented herein. The MEMS substrate comprises defined protrusions of respective distinct heights from a surface of the MEMS substrate, and the MEMS substrate is bonded to the CMOS substrate. In an aspect, the defined protrusions can be formed from the MEMS substrate. In another aspect, the defined protrusions can be deposited on, or attached to, the MEMS substrate. In yet another aspect, the MEMS substrate comprises monocrystalline silicon and/or polysilicon. In yet even another aspect, the defined protrusions comprise respective electrodes of sensors of the device.

A method for producing a system, including a first microelectromechanical element and a second microelectromechanical element, including the following: providing, a substrate, having the first microelectromechanical element and the second microelectromechanical element, and a cap element, a getter material being situated on the substrate in a first region in a surrounding environment of the first microelectromechanical element and/or on the cap element in a first corresponding region; situating the cap element on the substrate using a wafer bonding technique so that a sealed first chamber is formed that contains the first microelectromechanical element and the first region and/or the first corresponding region, a sealed second chamber being formed that contains the second microelectromechanical element; producing an opening in the second chamber; and sealing the opening at a first ambient pressure, in particular a first gas pressure.

The sensor package comprises a carrier (1) including electric conductors (13), an ASIC device (6) and a sensor element (7), which is integrated in the ASIC device (6). A dummy die or interposer (4) is arranged between the carrier (1) and the ASIC device (6). The dummy die or interposer (4) is fastened to the carrier (1), and the ASIC device (6) is fastened to the dummy die or interposer (4).

Some embodiments of the present disclosure are related to an integrated chip including a first substrate underlying a second substrate. The first and second substrates at least partially define a cavity. An absorptive layer is disposed within the cavity and comprises a reactive mater. An absorption-enhancement layer is disposed along the absorptive layer and within the cavity. The absorption-enhancement layer is configured to pass the reactive material from a top surface to a bottom surface of the absorption-enhancement layer.