A method for conditioning a polishing pad, which is configured to polish a wafer and attached to a rotatable discoid turntable, by using a conditioning head, the method being characterized by: moving the conditioning head in a radial direction of the turntable to perform the conditioning while rotating the polishing pad attached to the turntable by rotation of the turntable; and controlling a rotational speed of the turntable and a moving speed of the conditioning head in the radial direction of the turntable in correspondence with a distance of the conditioning head from a center of the turntable. Consequently, the method for conditioning a polishing pad which enables appropriately conditioning an entire polishing surface of the polishing pad can be provided.

A {100} indium phosphide (InP) wafer with pits distributed on the back side thereof, a method and an etching solution for manufacturing thereof are provided, wherein the pits on the back side have an elongated shape with a maximum dimension of the long axis of 65 m, and the pits have a maximum depth of 6.0 m. The {100} indium phosphide (InP) wafer has controllable pits distribution on the back side, thus provide a controllable emissivity of the wafer back side surface for better control of wafer back side heating during the epitaxial growth.

A {100} indium phosphide (InP) wafer with pits distributed on the back side thereof, a method and an etching solution for manufacturing thereof are provided, wherein the pits on the back side have an elongated shape with a maximum dimension of the long axis of 65 m, and the pits have a maximum depth of 6.0 m. The {100} indium phosphide (InP) wafer has controllable pits distribution on the back side, thus provide a controllable emissivity of the wafer back side surface for better control of wafer back side heating during the epitaxial growth.

The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from 1.0 m to 1.0 m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm.sup.2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm.sup.2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm.sup.2 or higher.

The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from 1.0 m to 1.0 m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm.sup.2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm.sup.2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm.sup.2 or higher.

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation 1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation 1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less.

Semiconductor wafers, are processed, using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.

Example features relate to a method of polishing a chamfered wafer surface, the method including beveling a wafer to generate the chamfered wafer surface, the chamfered wafer surface being inclined with respect to a main wafer surface by an angle ; and polishing the chamfered wafer surface with a polishing pad, a polishing surface of the polishing pad being inclined with respect to the chamfered wafer surface by an angle ; wherein the angle is equal to or smaller than the angle . Example features relate to a system for polishing the chamfered surface, the system including a polishing pad mounting jig configured to polish the chamfered surface, an angle being defined between the chamfered surface and the main surface; and a polishing pad in contact with the chamfered surface at an angle during polishing; wherein the angle is smaller than the angle .

Example features relate to a method of polishing a chamfered wafer surface, the method including beveling a wafer to generate the chamfered wafer surface, the chamfered wafer surface being inclined with respect to a main wafer surface by an angle ; and polishing the chamfered wafer surface with a polishing pad, a polishing surface of the polishing pad being inclined with respect to the chamfered wafer surface by an angle ; wherein the angle is equal to or smaller than the angle . Example features relate to a system for polishing the chamfered surface, the system including a polishing pad mounting jig configured to polish the chamfered surface, an angle being defined between the chamfered surface and the main surface; and a polishing pad in contact with the chamfered surface at an angle during polishing; wherein the angle is smaller than the angle .