A polishing material which controls a polishing rate of a silicon surface is provided. A polishing material including abrasive grains and a compound represented by a Formula (1).

R—O-(AO).sub.m—H  Formula (1)

In the Formula (1), R is an organic group including a conjugated system and may include a heteroatom in a carbon skeleton, and C1/(C1+C2)≥0.4 holds, where C1 is the number of atoms constituting the conjugated system and C2 is the number of atoms not constituting the conjugated system among atoms constituting the carbon skeleton,

AO represents an oxyalkylene group, and a plurality of the AOs may be the same as or different from each other, and

n is an integer of 2 to 200.

In a method of producing a bonded wafer, the amount of depression of the polishing cloth is 50 μm to 90 μm, and the surface hardness (ASKER C) of the polishing cloth is 50 to 60. In the bonded wafer, the polycrystalline silicon layer has a thickness variation Δt of 5% or less, and the support substrate wafer has a GBIR of 0.2 μm or less and an SFQR of 0.06 μm or less after the polycrystalline silicon layer is polished.

In the composition according to an embodiment, the weight ratio of toluene 2,4-diisocyanate in which one NCO group is reacted and unreacted toluene 2,6-diisocyanate in the urethane-based prepolymer is adjusted, whereby such physical properties as gelation time can be controlled. Thus, the polishing rate and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled while it has a hardness suitable for a soft pad, whereby it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

In the composition according to an embodiment, the weight ratio of toluene 2,4-diisocyanate in which one NCO group is reacted and unreacted toluene 2,6-diisocyanate in the urethane-based prepolymer is adjusted, whereby such physical properties as gelation time can be controlled. Thus, the polishing rate and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled while it has a hardness suitable for a soft pad, whereby it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.

The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.

The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.

The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.

Embodiments herein generally relate to polishing pads and method of forming polishing pads. In one embodiment, a polishing pad having a polishing surface that is configured to polish a surface of a substrate is provided. The polishing pad includes a polishing layer. At least a portion of the polishing layer comprises a continuous phase of polishing material featuring a plurality of first regions having a first pore-feature density and a plurality of second regions having a second pore-feature density that is different from the first pore-feature density. The plurality of first regions are distributed in a pattern in an X-Y plane of the polishing pad in a side-by-side arrangement with the plurality of second regions and individual portions or ones of the plurality of first regions are interposed between individual portions or ones of the plurality of second regions.

Embodiments herein generally relate to polishing pads and method of forming polishing pads. In one embodiment, a polishing pad having a polishing surface that is configured to polish a surface of a substrate is provided. The polishing pad includes a polishing layer. At least a portion of the polishing layer comprises a continuous phase of polishing material featuring a plurality of first regions having a first pore-feature density and a plurality of second regions having a second pore-feature density that is different from the first pore-feature density. The plurality of first regions are distributed in a pattern in an X-Y plane of the polishing pad in a side-by-side arrangement with the plurality of second regions and individual portions or ones of the plurality of first regions are interposed between individual portions or ones of the plurality of second regions.