An ultrasonic sensor includes: an element storage case including a case-side diaphragm having a thickness direction along a directional axis; and an ultrasonic element accommodated in the element storage case and spaced apart from the case-side diaphragm. The ultrasonic element includes an element-side diaphragm having the thickness direction along the directional axis and provided by a thin part of a semiconductor substrate. The semiconductor substrate is arranged to provide a closed space between the case-side diaphragm and the element-side diaphragm. The semiconductor substrate is fixed and supported by the element-storage case.

In a semiconductor device, a first substrate and a second substrate are bonded to each other through an insulating film. A hermetically sealed chamber is provided between the first substrate and the second substrate, and a sensing part is enclosed in the hermetically sealed chamber. The second substrate has a through hole penetrating in a stacking direction of the first substrate and the second substrate and exposing the first surface of the first substrate. A penetrating electrode is disposed on a wall surface of the through hole of the second substrate, and is electrically connected to the sensing part. A discharge path is provided, at a position located between the hermetically sealed chamber and the through hole for releasing outgas generated during bonding from the hermetically sealed chamber to the through hole.

In described examples, a first metal layer is arranged along a periphery of a cavity to be formed between a first substrate and a second substrate. A second metal layer is arranged adjacent to the first metal layer, where the second metal layer includes a cantilever. The cantilever is arranged to deform in response to forces applied from a contacting structure of the second substrate during bonding of the first substrate to the second substrate. The deformed cantilevered is arranged to impede contaminants against contacting an element within the cavity.

A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.

A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.

A sealing structure with a surface of a base material with a through-hole, an underlying metal film, and a sealing member bonded to the underlying metal film to seal the through-hole. The sealing member includes a compressed product of a metal powder including gold having a purity of 99.9% by mass or more and a lid-like metal film including a bulk-like metal including gold and having a thickness of not less than 0.01 m and not more than 5 m. The sealing material includes an outer periphery-side densified region in contact with an underlying metal film and a center-side porous region in contact with the through-hole. The shape of pores in the densified region is specified, and the horizontal length (l) of a pore in the radial direction at any cross-section of the densified region and the width (W) of the densified region satisfy the relationship of l0.1W.

An electronic device includes a package substrate, a circuit assembly, and a housing. The circuit assembly is mounted on the package substrate. The circuit assembly includes a first sealed cavity formed in a device substrate. The housing is mounted on the package substrate to form a second sealed cavity about the circuit assembly.

A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.

In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.

Accelerometer including a decoupling structure for fixing the accelerometer on a package and a MEMS sensor chip for measuring an acceleration. The chip is supported by the decoupling structure and includes a sensor wafer layer of a semiconductor material. The decoupling structure forms a bottom portion for fixing the decoupling structure on the package and a top portion fixed to the sensor wafer layer so that the chip is arranged above the decoupling structure. A width of the top portion in a planar direction is smaller than a width of the bottom portion and/or the sensor wafer layer in the planar direction. The decoupling structure is made of the same semiconductor material as the sensor wafer layer. The centre point of the top portion is arranged in a central region of the bottom portion. The chip includes a hermetically closed cavity which includes a seismic mass of the chip.