A semiconductor device includes a semiconductor chip including a chip substrate and a MEMS element, wherein the chip substrate includes a first surface and a second surface arranged opposite to the first surface, and wherein the MEMS element is disposed at the first surface of the chip substrate and the MEMS element includes a sensitive area; at least one electrical interconnect structure electrically connected to the first surface of the chip substrate; a chip carrier electrically connected to the at least one electrical interconnect structure; a flexible film provided over the second surface of the chip substrate to form a pocket in which the semiconductor chip resides; and a compressible material arranged between the second surface of the chip substrate and the flexible film.

A semiconductor device includes a semiconductor chip including a substrate and a MEMS element, wherein the substrate includes a surface, and wherein the MEMS element is disposed at the surface of the substrate and the MEMS element includes a sensitive area; a first electrical interconnect structure electrically connected to the surface of the substrate; a carrier electrically connected to the first electrical interconnect structure; and a first stress relieve spring entrenched in the carrier, wherein the first stress relieve spring is a single integral channel that comprises two parallel channels that join together at a periphery of the first electrical interconnect structure to form the single integral channel that wraps around a portion of the periphery of the first electrical interconnect structure, wherein the two parallel channels extend outward, in parallel, from the periphery of the first electrical interconnect structure to a first termination region of the carrier.

An integrated device package is disclosed. The package can include a carrier and an integrated device die having a front side and a back side. A mounting structure can serve to mount the back side of the integrated device die to the carrier. The mounting structure can comprise a first layer over the carrier and a second element between the back side of the integrated device die and the first layer. The first layer can comprise a first insulating material that adheres to the carrier, and the second element can comprise a second insulating material.

An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.

A process for fabricating a device for detecting electromagnetic radiation, including an encapsulation structure including an encapsulation layer on which a relief rests, and a sealing layer, which has a local breakage in continuity at the relief.

A semiconductor device includes a semiconductor chip including a substrate and a MEMS element, wherein the substrate includes a surface, and wherein the MEMS element is disposed at the surface of the substrate and the MEMS element includes a sensitive area; a first electrical interconnect structure electrically connected to the surface of the substrate; a carrier electrically connected to the first electrical interconnect structure; and a first stress relieve spring entrenched in the carrier, wherein the first stress relieve spring is a single integral channel that comprises two parallel channels that join together at a periphery of the first electrical interconnect structure to form the single integral channel that wraps around a portion of the periphery of the first electrical interconnect structure, wherein the two parallel channels extend outward, in parallel, from the periphery of the first electrical interconnect structure to a first termination region of the carrier.

A semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; and a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate. The semiconductor device further includes at least one electrical interconnect structure electrically connected to the first surface of the substrate, and a flexible carrier electrically connected to the at least one electrical interconnect structure, where the flexible carrier wraps around the semiconductor chip and extends over the second surface of the substrate such that a folded cavity is formed around the semiconductor chip.

A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.

A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.

A semiconductor device includes a first region; a second region that is peripheral to the first region; a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed in the first region at the first surface of the substrate; a back end of line (BEOL) stack disposed on the first surface of the semiconductor chip that extends laterally from the MEMS element, in the first region, into the second region; a first cavity formed in the BEOL stack that exposes the sensitive area of the stress-sensitive sensor, wherein the first cavity extends entirely through the BEOL stack over the first region thereby exposing a sensitive area of the stress-sensitive sensor; and at least one stress-decoupling trench laterally spaced from the stress-sensitive sensor and laterally spaced from the first cavity with a portion of the BEOL stack interposed between.