A pressure sensor comprises a first substrate and a cap attached to the first substrate. The cap includes a processing circuit, a cavity and a deformable membrane separating the cavity and a port open to an outside of the pressure sensor. Sensing means are provided for converting a response of the deformable membrane to pressure at the port into a signal capable of being processed by the processing circuit. The cap is attached to the first substrate such that the deformable membrane faces the first substrate and such that a gap is provided between the deformable membrane and the first substrate which gap contributes to the port. The first substrate comprises a support portion the cap is attached to, a contact portion for electrically connecting the pressure sensor to an external device, and one or more suspension elements for suspending the support portion from the contact portion.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, wherein the stress-sensitive sensor is sensitive to mechanical stress; a first pair of adjacent stress-decoupling trenches arranged laterally from a first lateral side of the stress-sensitive sensor, where each stress-decoupling trench of the first pair of adjacent stress-decoupling trenches extends partially from the first surface into the substrate towards the second surface although not completely to the second surface; and a first spring structure formed between the first pair of adjacent stress-decoupling trenches such that the first spring structure is arranged laterally from the stress-sensitive sensor and is configured to absorb external stress from an environment.

A semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; and a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate. The semiconductor device further includes at least one electrical interconnect structure electrically connected to the first surface of the substrate, and a flexible carrier electrically connected to the at least one electrical interconnect structure, where the flexible carrier wraps around the semiconductor chip and extends over the second surface of the substrate such that a folded cavity is formed around the semiconductor chip.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, wherein the stress-sensitive sensor is sensitive to mechanical stress; a first pair of adjacent stress-decoupling trenches arranged laterally from a first lateral side of the stress-sensitive sensor, where each stress-decoupling trench of the first pair of adjacent stress-decoupling trenches extends partially from the first surface into the substrate towards the second surface although not completely to the second surface; and a first spring structure formed between the first pair of adjacent stress-decoupling trenches such that the first spring structure is arranged laterally from the stress-sensitive sensor and is configured to absorb external stress from an environment.

A semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; and a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate. The semiconductor device further includes at least one electrical interconnect structure electrically connected to the first surface of the substrate, and a flexible carrier electrically connected to the at least one electrical interconnect structure, where the flexible carrier wraps around the semiconductor chip and extends over the second surface of the substrate such that a folded cavity is formed around the semiconductor chip.

An apparatus includes a sensor assembly and a housing assembly. The sensor assembly may have (i) a package surrounding a sensor and (ii) a plurality of terminals integrated with the package. The housing assembly may have (i) a first cavity configured to receive the sensor assembly, (ii) a second cavity configured to receive an electrical connector, (iii) a plurality of ports in communication between the first cavity and the second cavity and (iv) a location feature configured to orient the housing assembly while the housing assembly is mounted to a structure. At least one rib may apply at least one force on the sensor assembly to hold the sensor assembly in the first cavity. The sensor may be outside a plane of the force. The terminals may extend through the ports from the first cavity to the second cavity.

A semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; and a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate. The semiconductor device further includes at least one electrical interconnect structure electrically connected to the first surface of the substrate, and a flexible carrier electrically connected to the at least one electrical interconnect structure, where the flexible carrier wraps around the semiconductor chip and extends over the second surface of the substrate such that a folded cavity is formed around the semiconductor chip.

An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.

A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.

An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.