The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

A sensor component having a MEMS sensor and an ASIC for one sensor function each. A base element, a wall element in the form of a frame and a cover together enclose a cavity of a housing. The MEMS sensor is mounted inside the cavity on the base element of the housing. The ASIC has an active sensor surface and is mounted on or under the cover or is embedded in the cover. Electrical external contacts for the MEMS sensor and ASIC are provided on an external surface of the housing. The cavity has at least one opening or bushing.

A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.

A wafer level package comprises a functional wafer with a first surface, device structures connected to device pads arranged on the first surface. A cap wafer, having an inner and an outer surface, is bonded with the inner surface to the first surface of the functional wafer. A frame structure surrounding the device structures is arranged between functional wafer and cap wafer. Connection posts are connecting the device pads on the first surface to inner cap pads on the inner surface. Electrically conducting vias are guided through the cap wafer connecting inner cap pads on the inner surface and package pads on the outer surface of the cap wafer.

A package and method of packaging for integrated microfluidic devices and systems is disclosed wherein a package is made from individually processed and patterned layers of LTCC green tape, that is aligned and stacked, and then co-fired to form a stable LTCC ceramic packaging modules. Subsequently, microfluidic device die and/or integrated microfluidic systems device die are bonded to pre-determined areas of the packaging modules and the modules are aligned bonded together to form leak-free, sealed packages for the microfluidic devices and systems. The use of LTCC materials and techniques provides a low-cost flexible and easily customizable packaging approach for microfluidic devices and systems that can be designed and transitioned into production with significant development time and cost.

An electrical contacting between a surrounding wiring and a conductor region. The conductor region is situated in a conductor layer above an SOI wafer or SOI chip. A cover layer is situated above the conductor layer and below the surrounding wiring. The cover layer has a contacting region. The contacting region is insulated from the rest of the cover layer by a first configuration of recesses. An opening is formed at least in the contacting region. A metallic material is situated in the opening. The metallic material connects the surrounding wiring and the conductor region.

The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover, and the MEMS microphone die is substrate-mounted and acoustically coupled to an acoustic port provided in the surface mount package. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.

A method is provided for sealing and contacting a microelectromechanical device that includes a silicon device wafer with MEMS device structures and a cap wafer with an electrical circuit. The device wafer includes a sealing region and an interconnection region. Moreover, the cap wafer includes a corresponding sealing region and an interconnection region. Layers of eutectic metal alloy material are deposited on the sealing and the interconnection regions of the device wafer and the cap wafer. The cap wafer is bonded to the device wafer so that the interconnection region of the device wafer is aligned with the interconnection region of the cap wafer and the sealing region of the device wafer is aligned with the sealing region of the cap wafer.

A packaged cavity structure includes an embedded packaging frame having a first cavity and a first conductive post respectively penetrating an insulation layer in a height direction, a chipset within the first cavity, a first circuit layer on an upper surface of the embedded packaging frame, a first dielectric layer on the first circuit layer, a second circuit layer on the first dielectric layer, a through-hole penetrating the first dielectric layer and the insulation layer, a third circuit layer on a lower surface of the embedded packaging frame, a support post enclosure on the third circuit layer, and a packaging layer formed along the outside of the support post enclosure. A second cavity communicating with the through-hole is formed between the packaging layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip provided in a back-to-back stack.