In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

A fullcover package solution in combination with copper pillars or solder bumps and acoustic cavities is proposed to provide maximum usable design area compared to current thin film acoustic wafer level packages. Manufacturing can be done in a self-aligned interconnection process.

A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.

An electronic device includes first and second semiconductor dies, the first semiconductor die having: a side extending in a first plane of orthogonal first and second directions; a sensor circuit along the side; and a conductive terminal extending outward from the side along an orthogonal third direction, and the second semiconductor die bonded to the first semiconductor die and having: a bottom side; a lateral side; and an insulation layer, the bottom side spaced apart from and facing the side of the first semiconductor die to form a protected chamber for the sensor circuit, the lateral side of the second semiconductor die spaced apart from the conductive terminal along the first direction, the insulation layer extending along the lateral side of the second semiconductor die, and the insulation layer spaced apart from and facing the conductive terminal along the first direction.

A fullcover package solution in comnination with copper pillars or solder bumps and acoustic cavities is propsed to provide maximum usable design area compared to current thin film acoustic wafer level packages. Manufacturing can be done in a self-aligned interconnection process.

There is provided a wafer level package (100) for a device comprising: a first substrate (104) and a second substrate (116); at least one ground line (102) on a surface of the first substrate (104); at least one lateral electrical connection line (106) on the first substrate (104); a seal ring (108) between the first substrate (104) and the second substrate (116), wherein the at least one ground line (102) is terminated at the seal ring (108) and the at least one lateral electrical connection line (106) is configured to extend through the seal ring (108) for creating an electrical connection between the device inside the package (100) and an electrical circuit outside the package (100), and the seal ring comprises a passage (110) configured extend to the at least one ground line (102) through the seal ring (108); a bonding layer (122) between the seal ring (108) and the second substrate (116) for bonding the second substrate with the first substrate (104), wherein the bonding layer (122) is configured to connect the second substrate (116) to the at least one ground line (102).