Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.

Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays of well-controlled, solid-state nanopores by a cyclic process including atomic layer deposition (ALD), or chemical vapor deposition (CVD), and etching. One or more features are formed in a thin film deposited on a topside of a substrate. A dielectric material is deposited over the substrate having the one or more features in the thin film. An etching process is then used to etch a portion of the dielectric material deposited over the substrate having the one or more features in the thin film. The dielectric material deposition and etching processes are optionally repeated to reduce the size of the features until a well-controlled nanopore is formed through the thin film on the substrate.

Methods are provided for manufacturing well-controlled, solid-state nanopores in close proximity and arrays thereof. In one embodiment, a plurality of wells and one or more channels are formed in a substrate. Each of the wells is adjacent a channel. A portion of a sidewall of each well is exposed. The portion of exposed sidewall is nearest to the adjacent channel. The portion of the exposed sidewall of each well is laterally etched towards the adjacent channel. A nanopore is formed connecting the wells to an adjacent channel.

A method of fabricating an electronic component includes forming a functional unit on a main surface of a substrate, forming a sacrificial layer covering the functional unit on the main surface, forming a cap layer covering the sacrificial layer, the cap layer forming a periphery enclosing the cavity on the main surface, forming holes through the cap layer, forming a cavity by removing the sacrificial layer using a wet etching process through the holes, the holes including a peripheral hole communicating an inside of the cavity with an outside of the cavity along the main surface, and forming a first resin layer covering the cap layer and the main surface.

A method of forming a semiconductor device includes following steps. First of all, plural first openings and plural second openings are sequentially formed on a material layer disposed on a substrate, with the second openings across the first openings to form plural overlapped regions. Then, plural patterns arranged in an array arrangement are formed, with each pattern overlapped each overlapped region, respectively. After that, transferring the first openings, the second openings and the patterns to the material layer, to from plural material patterns in an array arrangement. In another embodiment of the present invention, the first openings and the second openings may be replaced by plural first patterns and plural second patterns, while the patterns are replaced by plural openings.

A method for creating at least one recess, in particular an aperture, in a transparent or transmissive material, includes: selectively modifying the material along a beam axis by electromagnetic radiation; and creating the at least one recess by one or more etching steps, using different etching rates in a modified region and in non-modified regions. The electromagnetic radiation produces modifications having different characteristics in the material along the beam axis such that the etching process in the material is heterogeneous and the etching rates differ from one another in regions modified with different characteristics under unchanged etching conditions.

A MEMS microphone includes a substrate defining a cavity, a diaphragm being spaced apart from the substrate, covering the cavity, and being configured to generate a displacement thereof in response to an applied acoustic pressure, an anchor extending from an end portion of the diaphragm, the anchor including a lower surface in contact with an upper surface of the substrate to support the diaphragm, a back plate disposed over the diaphragm, the back plate being spaced apart from the diaphragm such that an air gap is maintained between the back plate and the diaphragm, and defining a plurality of acoustic holes and an upper insulation layer provided on the substrate, covering the back plate, and holding the back plate to space the back plate from the diaphragm, the upper insulation layer having a flat plate shape to prevent sagging of the back plate.

The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

There is provided a nozzle substrate including a nozzle hole penetrating in a thickness direction. The nozzle substrate includes a main substrate including a first surface and a second surface, an oxidation film formed on the second surface of the main substrate, and a water repellent film formed on a surface at an opposite side to the main substrate side of the oxidation film. The nozzle hole includes a first through hole penetrating the main substrate in a thickness direction, a second through hole penetrating the oxidation film and being connected to the first through hole, and a third through hole penetrating the water repellent film and being connected to the second through hole. An inner circumference surface of the second through hole and an inner circumference surface of the third through hole are approximately flush.

A first modulation voltage is applied to a thin film. An amount of a change in the phase of a current carried through the thin film with respect to the phase of the first modulation voltage is compared with a threshold. Upon detecting that the amount of the change in the phase exceeds the threshold is detected, the application of the first modulation voltage is stopped. Thus, a nanopore is formed on the thin film at high speed.