A method for forming electrical contacts on a semiconductor substrate is disclosed. The method includes forming a first metal layer over the substrate, and forming a layer of a second metal oxide by sputter deposition of a second metal in an oxygen environment. In some embodiments, the second metal oxide may be ruthenium dioxide, and the first metal layer may be gold, copper, platinum, silver or aluminum.

A method for forming a biological microdevice includes applying a biocompatible coarse scale additive process with an additive device and a biocompatible material to form an object. The coarse scale is a dimension not less than about 100 m. The method also includes applying a biocompatible fine scale subtractive process with a subtractive device to the object. The fine scale is a dimension not greater than about 1000 m. The method also includes moving the object between the additive device and the subtractive device. A system is also provided for performing the above method and includes the additive device, the subtractive device, a means for transporting the object between the additive device and subtractive device and a processor with a memory including instructions to perform one or more of the above method steps.

A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The MEMS device structure includes a micro-electro-mechanical system (MEMS) substrate, and a substrate formed over the MEMS substrate. The substrate includes a semiconductor via through the substrate. The MEMS device structure includes a dielectric layer formed over the substrate and a polymer layer formed on the dielectric layer. The MEMS device structure also includes a conductive layer formed in the dielectric layer and the polymer layer. The conductive layer is electrically connected to the semiconductor via, and the polymer layer is between the conductive layer and the dielectric layer.

A device and method utilizes interconnecting layers separated by an insulating layer. A layered structure comprises a first and a second layer of electrically conductive material, and a third layer of electrically insulating material between them. A via trench is fabricated that extends from the second layer through the third layer into the first layer, a surface on the first layer of electrically conductive material forming a bottom surface of the via trench. An ink-jetting set-up for a mixture of liquid carrier and nanoparticles of conductive material is formed, and a specific process period is determined. Capillary flow of nanoparticles to peripheral edges of an ink-jetted blob of said mixture is induced. The mixture is ink-jetted into a blob on the via trench; the layered structure is heated to evaporate the liquid carrier. The interconnection element is higher at a certain point than between opposing side walls.

Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.

A method for bonding and interconnecting micro-electronic components is provided. In one aspect, two substrates are bonded to form a 3D assembly of micro-electronic components. Both substrates include first cavities open to the respective bonding surfaces, and at least one substrate includes a second cavity that is larger than the first cavities in terms of its in-plane dimensions, and possibly also in terms of its depth. An electrically conductive layer is produced on each substrate. The layer is patterned in the second cavity, and a micro-electronic device is fabricated in the second cavity. The bonding surfaces are planarized, removing the conformal layer from the bonding surfaces, and the substrates are bonded to form the assembly, where the first cavities of both substrates are brought into mutual contact to form an electrical connection. Device in the large cavities may be contacted through TSV connections or back end of line interconnect levels.

The present invention generally relates to an RF MEMS DVC and a method for manufacture thereof. To ensure that undesired grain growth does not occur and contribute to an uneven RF electrode, a multilayer stack comprising an AlCu layer and a layer containing titanium may be used. The titanium diffuses into the AlCu layer at higher temperatures such that the grain growth of the AlCu will be inhibited and the switching element can be fabricated with a consistent structure, which leads to a consistent, predictable capacitance during operation.

The MEMS sensor includes: a device substrate on which a device pattern is formed; a cap substrate disposed on top of the device substrate, the cap substrate comprising a first cavity area; a base substrate disposed on the bottom of the device substrate; a first-through silicon via formed through the base substrate, the first-through silicon via including a first core area for outputting an electrical signal provided from the device pattern to the outside or transmitting an electrical signal provided from the outside to the device pattern, a first insulating area surrounding an outer surface of the first core area, a first peripheral area surrounding an outer surface of the first insulating area, and a second insulating area surrounding an outer surface of the first peripheral area; and a circuit board, electrically connected to the first-through silicon via, for processing electrical signals for the device pattern.

Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or dishing of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.