A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

A micro-electro-mechanical system (MEMS) package structure and a method for fabricating the MEMS package structure. The MEMS package structure includes a MEMS die (210,220) and a device wafer (100). The MEMS die (210,220) is arranged on a first surface (100a) of the device wafer and includes a closed micro-cavity (211,221) and a contact pad (212,222) configured to be coupled to an external electrical signal. In the device wafer (100), there are arranged a control unit and an interconnection structure (300) electrically connected to each of the contact pad (212,222) and the control unit. On a second surface (100b) of the device wafer, there is arranged a rewiring layer (400) electrically connected to the interconnection structure (300). According to the MEMS package structure fabrication method, arranging the MEMS die (210,220) and the rewiring layer (400) on opposing sides of the device wafer (100) is conducive to shrinkage of the MEMS package structure. In addition, the MEMS package structure allows the integration of a plurality of MEMS dies of the same or different structures and functions on the same device wafer.

The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.

A manufacturing method for a micromechanical component. The method includes: providing an ASIC component including first front and rear sides, a strip conductor unit being provided at the first front side; providing a MEMS component including second front and rear sides, a micromechanical functional element situated in a cavity at the second front side; bonding the first front side onto the second front side; back-thinning the first rear side; forming vias starting from the back-thinned first rear side and from a redistribution unit on the first rear side, the vias electrically connecting the strip conductor unit to the redistribution unit; forming electrical contact elements on the redistribution unit; and back-thinning the second rear side. The back-thinning of the first and second rear side taking place so that a thickness of the stack made up of ASIC component and MEMS component is less than 300 micrometers.

A sensor device includes a first and second Micro-Electro-Mechanical (MEM) structures. The first MEM structure includes a first heating element on a first layer of the first MEM structure. The first heating element includes an input adapted to receive an input signal. The first MEM structure also includes a first temperature sensing element on a second layer of the first MEM structure. The second MEM structure includes a second heating element on a first layer of the second MEM structure and a second temperature sensing element on a second layer of the second MEM structure. An output circuit has a first input coupled to the first temperature sensing element and a second input coupled to the second temperature sensing element.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a metallization layer over the substrate, and a sensing structure over the metallization layer. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier in proximity to a top surface of the outgassing layer, the patterned outgassing barrier exposing a portion of the outgassing layer, and an electrode over the patterned outgassing barrier. The method for manufacturing the semiconductor device is also provided.

An ultrasonic transducer includes a membrane, a bottom electrode, and a plurality of cavities disposed between the membrane and the bottom electrode, each of the plurality of cavities corresponding to an individual transducer cell. Portions of the bottom electrode corresponding to each individual transducer cell are electrically isolated from one another. Each portion of the bottom electrode corresponds to each individual transducer that cell further includes a first bottom electrode portion and a second bottom electrode portion, the first and second bottom electrode portions electrically isolated from one another.

An integrated package method for MEMS element and ASIC chip includes forming a re-layout layer on a front surface of an ASIC wafer; coating an organic compound layer on the re-layout layer and applying a lithography process to the organic compound layer to from a microcavity array; aligning and bonding an electrode connection pad layer on a front surface of an MEMS element with the microcavity array to form a closed cavity structure; thinning and exposing a silicon substrate on a back surface of the MEMS element to a desired thickness; applying the lithographic process on the MEMS element to expose the electrode connection pad layer and an electrical contact area of the re-layout layer; and manufacturing a metal connection member connected to the electrode connection pad layer and the electrical contact area. An integrated package structure for MEMS element and ASIC chip is also provided.