A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

A method for bonding two substrates is described, comprising providing a first and a second silicon substrate, providing a raised feature on at least one of the first and the second silicon substrate, forming a layer of gold on the first and the second silicon substrates, and pressing the first substrate against the second substrate, to form a thermocompression bond around the raised feature. The high initial pressure caused by the raised feature on the opposing surface provides for a hermetic bond without fracture of the raised feature, while the complete embedding of the raised feature into the opposing surface allows for the two bonding planes to come into contact. This large contact area provides for high strength.

A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.

A method for encapsulating a microelectronic device, arranged on a support substrate, with an encapsulation cover includes, inter alia, the following sequence of steps: a) providing a support substrate on which a microelectronic device is arranged, b) depositing a bonding layer on the first face of the substrate, around the microelectronic device, c) positioning an encapsulation cover on the bonding layer in such a way as to encapsulate the microelectronic device, d) thinning the second main face of the support substrate and the second main face of the encapsulation cover by chemical etching.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

A process for manufacturing a packaged microelectromechanical device includes: forming a lid having a face and a cavity open on the face; coating the face of the lid and walls of the cavity with a metal layer containing copper; and coating the metal layer with a protective layer.

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

A configuration for a capacitive pressure sensor uses a silicon on insulator wafer to create an electrically isolated sensing node across a gap from a pressure sensing wafer. The electrical isolation, small area of the gap, and silicon material throughout the capacitive pressure sensor allow for minimal parasitic capacitance and avoid problems associated with thermal mismatch.

In described examples, a transient liquid phase (TLP) metal bonding material includes a first substrate and a base metal layer. The base metal layer is disposed over at least a portion of the first substrate. The base metal has a surface roughness (Ra) of between about 0.001 to 500 nm. Also, the TLP metal bonding material includes a first terminal metal layer that forms an external surface of the TLP metal bonding material. A metal fuse layer is positioned between the base metal layer and the first terminal metal layer. The TLP metal bonding material is stable at room temperature for at least a predetermined period of time.

A method of fabricating a micro electro mechanical system (MEMS) structure includes providing a first substrate structure including a bonding pad structure. The bonding pad structure has at least one recess therein. A second substrate structure is provided and bonded with the bonding pad structure of the first substrate structure.