A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.

Methods are disclosed to prepare permanent materials that can be coated onto microelectronic substrates or used for other structural or optical applications. The permanent materials are thermally stable to at least 300° C., cure using a photo or thermal process, exhibit good chemical resistance (including during metal passivation), and have a lifespan of at least 5 years, preferably at least 10 years, in the final device. Advantageously, these materials can also be bonded at room temperature. The materials exhibit no movement or squeeze-out after bonding and adhere to a variety of substrate types. A chip-to-chip, chip-to-wafer, and/or wafer-to-wafer bonding method utilizing this material is also described.

Embodiments of the disclosure provide methods of bonding silicon wafers. An exemplary method may include cleaning the silicon wafers to remove residues. The method may also include performing a hydrophilic treatment to surfaces of the silicon wafers to increase surface energy. The method may also include pre-bonding the silicon wafers at room temperature. In addition, the method may include performing a rapid thermal annealing treatment to the pre-bonded silicon wafers to bond the silicon wafers.

A micro-electro-mechanical pressure sensor device, formed by a cap region and by a sensor region of semiconductor material. An air gap extends between the sensor region and the cap region; a buried cavity extends underneath the air gap, in the sensor region, and delimits a membrane at the bottom. A through trench extends within the sensor region and laterally delimits a sensitive portion housing the membrane, a supporting portion, and a spring portion, the spring portion connecting the sensitive portion to the supporting portion. A channel extends within the spring portion and connects the buried cavity to a face of the second region. The first air gap is fluidically connected to the outside of the device, and the buried cavity is isolated from the outside via a sealing region arranged between the sensor region and the cap region.

A vibrational sensor comprises a microelectromechanical (MEMS) microphone having a base and a lid defining an enclosure, a MEMS acoustic pressure sensor within the enclosure, and a port defining an opening through the enclosure and material that is arranged to plug the port of the MEMS microphone. In embodiments, the MEMS microphone further includes an integrated circuit within the enclosure that is electrically connected to the MEMS acoustic pressure sensor. In some embodiments, the integrated circuit is configured to bias and buffer the MEMS acoustic pressure sensor. In these and other embodiments, the integrated circuit includes circuitry for conditioning and processing electrical signals generated by the MEMS acoustic pressure sensor. In embodiments, the material is arranged with respect to the port so as to cause the MEMS acoustical pressure sensor to sense vibrational energy rather than acoustic energy as in a conventional MEMS microphone.

An apparatus for the wafer level packaging (WLP) of micro-bolometer vacuum package assemblies (VPAs), in one embodiment, includes a wafer alignment and bonding chamber, a bolometer wafer chuck and a lid wafer chuck disposed within the chamber in vertically facing opposition to each other, means for creating a first ultra-high vacuum (UHV) environment within the chamber, means for heating and cooling the bolometer wafer chuck and the lid wafer chuck independently of each other, means for moving the lid wafer chuck in the vertical direction and relative to the bolometer wafer chuck, means for moving the bolometer wafer chuck translationally in two orthogonal directions in a horizontal plane and rotationally about a vertical axis normal to the horizontal plane, and means for aligning a fiducial on a bolometer wafer held by the bolometer wafer chuck with a fiducial on a lid wafer held by the lid wafer chuck.

An apparatus and method for wafer-level hermetic packaging of MicroElectroMechanical Systems (MEMS) devices of different shapes and form factors is presented in this disclosure. The method is based on bonding a glass cap wafer with fabricated micro-glassblown “bubble-shaped” structures to the substrate glass/Si wafer. Metal traces fabricated on the substrate wafer serve to transfer signals from the sealed cavity of the bubble to the outside world. Furthermore, the method provides for chip-level packaging of MEMS three dimensional structures. The packaging method utilizes a micro glass-blowing process to create “bubbleshaped” glass lids. This new type of lids is used for vacuum packaging of three dimensional MEMS devices, using a standard commercially available type of package.

A semiconductor device includes a substrate structure. The substrate structure includes a protruding engagement member having an inner periphery defining a groove and an outer periphery, an oxide layer on the protruding engagement member, and a bonding material layer on the oxide layer. The semiconductor device also includes a micro-electromechanical system (MEMS) substrate having a bonging pad. The bonding pad of the MEMS substrate is bonded to the bonding material layer of the substrate structure.

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.