Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

The present application provides the block copolymers and their application. The block copolymer has an excellent self assembling property and phase separation and various required functions can be freely applied thereto as necessary.

The present disclosure provides methods of manufacturing porous silicon structures having controlled sizes, shapes, and porosity by using a series of protective layers and selective etching steps. A benefit of the methods disclosed herein can be providing microfabrication and nanofabrication methods that are capable of provide porous silicon structures having sizes, shapes, and porosity that are more tightly controlled by avoiding inadvertently etching parts of the silicon structures during the fabrication process.

A method includes masking a carbon-containing single crystal for defining masked regions and unmasked regions on the single crystal. The method also includes performing a plasma etch for removing portions of the unmasked regions of the single crystal, thereby defining a pillar in each unmasked region, and performing a chemical etch on the pillars at a temperature between 1200 C. and 1600 C. for selectively reducing a width of each pillar.

A MEMS package includes a wafer with an interconnect layer. A first device layer includes a first MEMS device having a first thickness, is disposed on the wafer and bonded to the interconnect layer. A second device layer includes a second MEMS device having a second thickness thinner than the first thickness, is laterally spaced apart from the first device layer, disposed on the wafer and bonded to the interconnect layer. A first cap substrate with a first cavity is bonded to the first device layer. The first MEMS device corresponds to the first cavity. A second cap substrate with a second cavity is laterally spaced apart from the first cap substrate and bonded to the second device layer. The second MEMS device corresponds to the second cavity.

The present disclosure provides an etching method that includes a resist pattern-forming step of forming a resist layer on a target object, the resist layer being formed of a resin, the resist layer having a resist pattern; an etching step of etching the target object via the resist layer having the resist pattern; and a resist protective film-forming step of forming a resist protective film on the resist layer. The etching step is repetitively carried out multiple times. A processing gas, used in the resist protective film-forming step, includes a gas capable of forming Si.sub.xO.sub.y.sub.z; wherein a is any one of F, Cl, H, and C.sub.kH.sub.l; and each of x, y, z, k, is a selected non-zero value. After the etching steps are repetitively carried out multiple times, the resist protective film-forming step is performed.

The present disclosure provides methods of manufacturing porous silicon structures having controlled sizes, shapes, and porosity by using a series of protective layers and selective etching steps. A benefit of the methods disclosed herein can be providing microfabrication and nanofabrication methods that are capable of provide porous silicon structures having sizes, shapes, and porosity that are more tightly controlled by avoiding inadvertently etching parts of the silicon structures during the fabrication process.

The present disclosure provides methods of manufacturing porous silicon structures having controlled sizes, shapes, and porosity by using a series of protective layers and selective etching steps. A benefit of the methods disclosed herein can be providing microfabrication and nanofabrication methods that are capable of provide porous silicon structures having sizes, shapes, and porosity that are more tightly controlled by avoiding inadvertently etching parts of the silicon structures during the fabrication process.

A method for wafer treatment is disclosed. A wafer is provided with a main surface, a surface layer, and a base layer. The surface layer is disposed between the main surface and the base layer, and the surface layer covers the base layer and exposes the main surface. Then, at least one laser process is performed to fully irradiate the main surface and the surface layer with a first laser to generate a plurality of optimized regions in the main surface and the surface layer, so that the optimized regions form at least one stress-relieving array.

A method for singulating a wafer having a first surface and a second surface situated opposite the first surface is disclosed. The method includes the following steps: contacting the wafer with a protective device having one or a plurality of carrying structures such that the first surface of the wafer is in contact with the plurality of carrying structures, singulating the wafer that is in contact with the protective device into a plurality of chips, and removing the chips from the wafer that is in contact with the protective device. Furthermore, a protective device having one or a plurality of carrying structures for temporarily carrying a wafer is disclosed. The protective device is configured to be used in the method disclosed herein.