A method of manufacturing a Fabry-Perot interference filter includes a forming step of forming a first thinned region, a first mirror layer, a sacrificial layer, and a second mirror layer are formed on a first main surface of a wafer, and the first thinned region in which at least one of the first mirror layer, the sacrificial layer, and the second mirror layer is partially thinned along each of a plurality of lines is formed; a cutting step of cutting the wafer into a plurality of substrates along each of the plurality of lines by forming a modified region within the wafer along each of the plurality of lines through irradiation of a laser light, after the forming step; and a removing step of removing a portion from the sacrificial layer through etching, between the forming step and the cutting step or after the cutting step.

The Fabry-Perot interference filter includes: a substrate having a first surface, a first laminate having a first mirror portion disposed on the first surface, a second laminate having a second mirror portion facing the first mirror portion with an air gap interposed therebetween, and an intermediate layer defining the air gap between the first and second laminate. The substrate has an outer edge portion positioned outside an outer edge of the intermediate layer when viewed from a direction perpendicular to the first surface. The second laminate further includes a covering portion covering the intermediate layer and a peripheral edge portion positioned on the first surface in the outer edge portion. The second mirror portion, the covering portion, and the peripheral edge portion are integrally formed so as to be continuous with each other. The peripheral edge portion is thinned along an outer edge of the outer edge portion.

A method of manufacturing a wiring board, includes forming an interconnect layer on a first insulating layer, roughening a surface of the interconnect layer, not in contact with the first insulating layer, to form concavo-convex portions, forming a bond enhancing film on the concavo-convex portions, partially removing the bond enhancing film, using an acid solution, and forming a second insulating layer on the first insulating layer, to cover the interconnect layer.

Double-patterning methods for build-up metallization features suitable for IC package assemblies. Double-patterned metallization features may, for example, achieve approximately twice the aspect ratio of single patterned metallization features for a given photolithography technology node. High aspect ratio metallization features may include a top feature portion that is over a bottom feature portion. The top and bottom portions each have a distinct sidewall slope indicative of their double-patterning. A hybrid plating mask may be employed during a metallization plating process. The hybrid mask may include multiple layers of photoresist to reach a desired mask thickness. Multiple exposures may be performed to incrementally image the hybrid plating mask, thereby maintaining better resolution for each exposure. In some exemplary embodiments, one layer of the hybrid plating mask has a negative photoresist composition into which features may be hardened through a first exposure, while another layer of the hybrid plating mask has a positive photoresist composition from which features may retained by protecting them from a second exposure.

The invention relates to a method of manufacturing a plurality of resonators, each formed by a membrane sealing a cavity, the method comprises: a) a step to form a plurality of cavities, advantageously identical, starting from one face called the front face of a support substrate, the plurality of cavities comprise central cavities and peripheral cavities arranged around the assembly formed by the central cavities; b) a step to form membranes, called central membranes and peripheral membranes respectively, covering central cavities and peripheral cavities respectively, by the transfer of a coverage film on the front face of the support substrate; c) a step to remove at least part of the peripheral membranes.

The present disclosure relates to a device for analyzing a fluid sample. In one aspect, the device includes a fluidic substrate that comprises a micro-fluidic component embedded in the fluidic substrate configured to propagate a fluid sample via capillary force through the device and a means for providing a fluid sample connected to the micro-fluidic component. The device also includes a lid attached to the fluidic substrate at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component. The fluidic substrate may be a silicon fluidic substrate and the lid may be a CMOS chip. In another aspect, embodiments of the present disclosure relate to a method for fabricating such a device, and the method may include providing a fluidic substrate, providing a lid, and attaching, through a CMOS compatible bonding process, the fluidic substrate to the lid to close the fluidic substrate at least partly.

An embodiment includes a method of texturing a semiconductor substrate, a semiconductor substrate manufactured using the method, and a solar cell including the semiconductor substrate, the method including: forming metal nanoparticles on a semiconductor substrate, primarily etching the semiconductor substrate, removing the metal nanoparticles, and secondarily etching the primarily etched semiconductor substrate to form nanostructures.

Methods for forming an electrode structure, which can be used as a biosensor, are provided in which the electrode structure has non-random topography located on one surface of an electrode base. In some embodiments, an electrode structure is obtained that contains no interface between the non-random topography of the electrode structure and the electrode base of the electrode structure. In other embodiments, electrode structures are obtained that have an interface between the non-random topography of the electrode structure and the electrode base of the electrode structure.

A method for manufacturing integrated IR (IR=infrared) emitter elements having an optical filter comprises back side etching through a carrier substrate, forming adhesive spacer elements on a conductive layer on the carrier substrate, placing a filter substrate having a filter carrier substrate and a filter layer on the adhesive spacer elements, fixing the adhesive spacer elements to the carrier substrate and the filter substrate by curing, pre-dicing through the filter substrate for exposing the contact pads of the structured conductive layer, and dicing through the frame structure in the carrier substrate for separating the integrated IR emitter elements having the optical filter.

Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.