A microelectromechanical systems (MEMS) package with high gettering efficiency is provided. A MEMS device is arranged over a logic chip, within a cavity that is hermetically sealed. A sensing electrode is arranged within the cavity, between the MEMS device and the logic chip. The sensing electrode is electrically coupled to the logic chip and is a conductive getter material configured to remove gas molecules from the cavity. A method for manufacturing the MEMS package is also provided.

A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an CMOS substrate or a combined MEMS and CMOS substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.

A method for providing a semiconductor layer arrangement on a substrate which comprises providing a semiconductor layer arrangement having a functional layer and a semiconductor substrate layer, attaching the semiconductor layer arrangement to a glass substrate layer such that the functional layer is arranged between the glass substrate layer and the semiconductor substrate layer, and removing the semiconductor substrate layer at least partially such that the glass substrate layer substitutes the semiconductor substrate layer as the substrate of the semiconductor layer arrangement.

A method of producing a semiconductor device includes providing a carrier structure having a semiconductor substrate; applying or introducing a precursor substance onto or into the carrier structure, treating the precursor substance for producing a porous matrix structure; introducing a functionalization substance into the porous matrix structure.

A method of forming a microphone device includes: forming a through-hole in a substrate wafer; providing a second wafer; bonding the second wafer to the substrate wafer; and forming a top electrode over a first surface of a single-crystal piezoelectric film of the second wafer. The second wafer may include the single-crystal piezoelectric film. The single-crystal piezoelectric film may have a first surface and an opposing second surface. The second wafer may further include a bottom electrode arranged adjacent to the second surface, and a support member over the single-crystal piezoelectric film. The through-hole in substrate wafer may be at least substantially aligned with at least one of the top electrode and the bottom electrode.

A method of manufacturing a MEMS device, the MEMS device comprising a movable Micro-Electro-Mechanical piezoelectric component and a CMOS circuit configured to be in conductive communication with the Micro-Electro-Mechanical component. A plurality of CMOS circuit layers are formed on a substrate to form the CMOS circuit, the plurality of CMOS circuit layers comprising a plurality of CMOS passivation and metallisation layers. A portion of at least one of the plurality of CMOS passivation and metallisation layers is removed in a component region of the device. One or more component region layers are formed in place of the removed portion in the component region to form the movable Micro-Electro-Mechanical piezoelectric component. The one or more component region layers are different from the portion of the at least one of the plurality of CMOS passivation and metallisation layers.

A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.

A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.