Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

A method of forming an ultrasonic transducer device involves depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.

An ultrasonic transducer device includes a patterned film stack disposed on first regions of a substrate, the patterned film stack including a metal electrode layer and a bottom cavity layer formed on the metal electrode layer. The ultrasonic transducer device further includes a planarized insulation layer disposed on second regions of the substrate layer, a cavity formed in a membrane support layer and a CMP stop layer, the CMP stop layer including a top layer of the patterned film stack and the membrane support layer formed over the patterned film stack and the planarized insulation layer. The ultrasonic transducer device also includes a membrane bonded to the membrane support layer. The CMP stop layer underlies portions of the membrane support layer but not the cavity.

A membrane is formed through processes including depositing a first piezoelectrical layer, depositing a first electrode layer over the first piezoelectrical layer, patterning the first electrode layer to form a first electrode, depositing a second piezoelectrical layer over the first electrode, depositing a second electrode layer over the second piezoelectrical layer, patterning the second electrode layer to form a second electrode, and depositing a third piezoelectrical layer over the second electrode. The third piezoelectrical layer, the second piezoelectrical layer, and the first piezoelectrical layer are etched to form a through-hole. The through-hole is laterally spaced apart from the first electrode and the second electrode. A first contact plug and a second contact plug are then formed to electrically connect to the first electrode and the second electrode, respectively.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.

Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device including a conductive bonding structure disposed between a substrate and a MEMS substrate. An interconnect structure overlies the substrate. The MEMS substrate overlies the interconnect structure and includes a moveable membrane. A dielectric structure is disposed between the interconnect structure and the MEMS substrate. The conductive bonding structure is sandwiched between the interconnect structure and the MEMS substrate. The conductive bonding structure is spaced laterally between sidewalls of the dielectric structure. The conductive bonding structure, the MEMS substrate, and the interconnect structure at least partially define a cavity. The moveable membrane overlies the cavity and is spaced laterally between sidewalls of the conductive bonding structure.

In a microelectromechanical component according to the invention, at least one microelectromechanical element (5), electrical contacting elements (3) and an insulation layer (2.2) and thereon a sacrificial layer (2.1) formed with silicon dioxide are formed on a surface of a CMOS circuit substrate (1) and the microelectromechanical element (5) is arranged freely movably in at least a degree of freedom. At the outer edge of the microelectromechanical component, extending radially around all the elements of the CMOS circuit, a gas- and/or fluid-tight closed layer (4) which is resistant to hydrofluoric acid and is formed with silicon, germanium or aluminum oxide is formed on the surface of the CMOS circuit substrate (1).

Disclose is a method for fabricating a semiconductor device. The method includes: forming a groove such as by etching one side surface of a first substrate; attaching a second substrate including a silicon layer on the etched surface of the first substrate formed with the hollow groove; etching the second substrate so as to leave substantially only the silicon layer; forming a thin film structure on the surface of silicon layers of the second substrate; and separating the second substrate formed with the thin film structure from the first substrate. For example, the groove structure may be formed in the lower portion of the device in the process of fabricating the semiconductor device to facilitate the final device separation.

A method for fabricating calcite channels in a nanofluidic device is described. A porous membrane is attached to a substrate. Calcite is deposited in porous openings in the porous membrane attached to the substrate. A width of openings in the deposited calcite is in a range from 50 to 100 nanometers (nm). The porous membrane is etched to remove the porous membrane from the substrate to form a fabricated calcite channel structure. Each channel has a width in the range from 50 to 100 nm.