Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.

Techniques for fabricating horizontally aligned nanochannels are provided. In one aspect, a method of forming a device having nanochannels is provided. The method includes: providing a SOI wafer having a SOI layer on a buried insulator; forming at least one nanowire and pads in the SOI layer, wherein the nanowire is attached at opposite ends thereof to the pads, and wherein the nanowire is suspended over the buried insulator; forming a mask over the pads, the mask having a gap therein where the nanowire is exposed between the pads; forming an alternating series of metal layers and insulator layers alongside one another within the gap and surrounding the nanowire; and removing the nanowire to form at least one of the nanochannels in the alternating series of the metal layers and insulator layers. A device having nanochannels is also provided.

Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

The present application relates to a micromechanical component (1) and a method for producing a micromechanical component (1). The proposed micromechanical component (1) comprises a layered structure and at least one piezoelectric element (10). The piezoelectric element (10) contains a first electrode (5) and second electrode (27) for generating and/or detecting deflections of a deflection element (16). The deflection element (16) is connected to a holder (17). The layered structure of the micromechanical component (1) comprises a silicon substrate (2), a conductive semiconductor layer (26), a piezoelectric layer (7) and a conductive layer film (12). The conductive semiconductor layer (26) forms the first electrode (5) and the conductive layer film (12) forms the second electrode (27) of the piezoelectric element, wherein the conductive semiconductor layer (26) at the same time forms a carrier layer (28) for the deflection element (16).

Techniques for fabricating horizontally aligned nanochannels are provided. In one aspect, a method of forming a device having nanochannels is provided. The method includes: providing a SOI wafer having a SOI layer on a buried insulator; forming at least one nanowire and pads in the SOI layer, wherein the nanowire is attached at opposite ends thereof to the pads, and wherein the nanowire is suspended over the buried insulator; forming a mask over the pads, the mask having a gap therein where the nanowire is exposed between the pads; forming an alternating series of metal layers and insulator layers alongside one another within the gap and surrounding the nanowire; and removing the nanowire to form at least one of the nanochannels in the alternating series of the metal layers and insulator layers. A device having nanochannels is also provided.

A method of manufacturing a semiconductor structure includes receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.

An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.

A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.