A semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a sensing structure disposed over the dielectric layer, a bonding structure disposed over the dielectric layer, a conductive layer covering the sensing structure, and a barrier layer disposed over the dielectric layer, the conductive layer and the bonding structure, wherein the conductive layer and the bonding structure are at least partially exposed from the barrier layer.

A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800 C. to 820 C.

Techniques for fabricating horizontally aligned nanochannels are provided. In one aspect, a method of forming a device having nanochannels is provided. The method includes: providing a SOI wafer having a SOI layer on a buried insulator; forming at least one nanowire and pads in the SOI layer, wherein the nanowire is attached at opposite ends thereof to the pads, and wherein the nanowire is suspended over the buried insulator; forming a mask over the pads, the mask having a gap therein where the nanowire is exposed between the pads; forming an alternating series of metal layers and insulator layers alongside one another within the gap and surrounding the nanowire; and removing the nanowire to form at least one of the nanochannels in the alternating series of the metal layers and insulator layers. A device having nanochannels is also provided.

A compound sensor includes a package, a first acceleration detector, a second acceleration detector, and an angular velocity detector. The first acceleration detector is disposed in a first cavity. The second acceleration detector is disposed in a second cavity. The angular velocity detector is disposed in a third cavity. An inner pressure of the first cavity is higher than an inner pressure of the second cavity. An inner pressure of the third cavity is lower than the inner pressure of the second cavity.

In an example, a method includes depositing an organic polymer layer on one or more material layers. The method also includes thermally curing the organic polymer layer. The method includes depositing a hard mask on the organic polymer layer and depositing a photoresist layer on the hard mask. The method also includes patterning the photoresist layer to expose at least a portion of the hard mask. The method includes etching the exposed portion of the hard mask to expose at least a portion of the organic polymer layer. The method also includes etching the exposed portion of the organic polymer layer to expose at least a portion of the one or more material layers.

A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800 C. to 820 C.

A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

According to at least one embodiment, methods of fabricating micro electro-mechanical systems (MEMS) structures involving lamination of an electromechanical layer to a micromechanical structure are disclosed.

Provided is a gas sensor including a substrate, a first membrane disposed on the substrate, a heating structure disposed on the first membrane, a second membrane disposed on the heating structure, a sensing electrode disposed on the second membrane, and a sensing material structure disposed on the sensing electrode. Here, the substrate provides an isolation space defined by a recessed surface obtained as a portion of a top surface of the substrate is spaced downward from a bottom surface of the first membrane, and the first membrane provides a first membrane etching hole that vertically extends to connect a top surface and the bottom surface of the first membrane and is connected with the isolation space. Also, the first membrane etching hole has a diameter of about 3 m to about 20 m.

A micro-electromechanical system (MEMS) electric field sensor using a resonant torsional shutter and a method of manufacturing the MEMS electric field sensor are described. A method of manufacturing a micro-electromechanical system (MEMS) electric field sensor according an embodiment includes: forming a metal layer on a wafer having a handle layer, a buried oxide layer arranged on the handle layer, and a device layer arranged on the buried oxide layer; patterning the metal layer to form a plurality of electrical pads thereon, forming a comb drive actuator on the device layer, the comb drive actuator including a sensing electrode and a torsional shutter configured to be resonant torsionally driven; forming a driving space of the torsional shutter in the handle layer; and etching and releasing the buried oxide layer.