Patent classifications
B81C2203/019
Semiconductor package and method for manufacturing the same
A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.
Semiconductor package with multiple compartments
A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.
MICROMECHANICAL DEVICE AND CORRESPONDING PRODUCTION METHOD
A micromechanical apparatus and a corresponding production method are described. The micromechanical apparatus encompasses a base substrate having a front side and a rear side; and a cap substrate, at least one surrounding trench having non-flat side walls being embodied in the front side of the base substrate; the front side of the base substrate and the trench being coated with at least one metal layer; the non-flat side walls of the trench being covered nonconformingly with the metal so that they do not form an electrical current path in a direction extending perpendicularly to the front side; and a closure, in particular a seal-glass closure, being embodied in the region of the trench between the base substrate and the cap substrate.
Method for closing off a micromechanical device by laser melting, and micromechanical device having a laser melt closure
A method is described for closing off a micromechanical device by laser melting, having the steps: (A) providing a micromechanical device having an access channel that has a collar at an external opening; (B) closing off the external opening of the access channel by laser irradiation of the collar, the collar being at least partly melted and the external opening being closed with melt made of a material of the collar. Also described is a micromechanical device having a laser melt closure, in particular produced by the method according to the present invention, the micromechanical device having an access channel that has a collar at an external opening, the external opening of the access channel being closed by a melt closure made of a material of the collar.
MEMS PACKAGE WITH ROUGHEND INTERFACE
A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.
ENCAPSULANT BARRIER
In described examples, a device mounted on a substrate includes an encapsulant. In at least one example, an encapsulant barrier is deposited along a scribe line, along which the substrate is singulatable. To encapsulate one or more terminals of the substrate, an encapsulant is deposited between the encapsulant barrier and an edge of the device parallel to the encapsulant barrier.
Package Comprising an Ion-Trap and Method of Fabrication
A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.
MEMS DEVICE AND FABRICATION METHOD THEREOF
A Micro-Electro-Mechanical System (MEMS) device includes a substrate, a packaging component provided on the substrate and a MEMS component provided inside the packaging component and on the substrate. The device further includes a sealing component. The sealing component is provided on the substrate and/or the packaging component, for preventing an external small molecule from contacting with the MEMS component.
Eutectic bonding with AlGe
A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.
Metal line design for hybrid-bonding application
A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.