Ultrasonic sensing approaches are described with integrated MEMS-CMOS implementations. Embodiments include ultrasonic sensor arrays for which PMUT structures of individual detector elements are at least partially integrated into the CMOS ASIC wafer. MEMS heating elements are integrated with the PMUT structures by integrating under the PMUT structures in the CMOS wafer and/or over the PMUT structures (e.g., in the protective layer). For example, embodiments can avoid wafer bonding and can reduce other post processing involved with conventional manufacturing of PMUT ultrasonic sensors, while also improving thermal response.

In an embodiment a pressure sensor device includes a substrate body, a pressure sensor having a membrane and a cap body having at least one opening, wherein the pressure sensor is arranged between the substrate body and the cap body in a vertical direction which is perpendicular to a main plane of extension of the substrate body, and wherein the mass of the substrate body amounts to at least 80% of the mass of the cap body and at most 120% of the mass of the cap body.

A method includes obtaining an active device layer. The active device layer has a first surface with one or more active feature areas. First portions of the active feature areas are exposed, and second portions of the active feature areas are covered by an insulating layer. A conformal overcoat layer is formed on the first surface. A base of a microelectromechanical systems (MEMS) device layer is formed on the conformal overcoat layer. The MEMS device layer is spatially segregated from the active feature areas by removing portions of the base of the MEMS device layer in one or more antiparasitic regions (APRs) that correspond to the active feature areas. Metal MEMS features are formed on the base of the MEMS device layer. Selected portions of the active feature areas are exposed removing portions of the conformal overcoat layer that overlay the active feature areas.

In described examples, a microelectromechanical system (MEMS) is located on a substrate. A silicon nitride (SiN) layer on a portion of the substrate. A mechanical structure has first and second ends. The first end is embedded in the SiN layer, and the second end is cantilevered from the SiN layer.

An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

Various embodiments of the present disclosure are directed towards an integrated chip including a microelectromechanical systems (MEMS) structure overlying a substrate. A capping structure overlies the MEMS structure. The capping structure at least partially defines a cavity. The MEMS structure is disposed in the cavity. An outgas structure adjacent to the cavity. The outgas structure comprises an amorphous material.

Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

A method of forming an ultrasonic transducer device involves depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.

An ultrasound transducer device includes an electrode, a membrane, and vias. The membrane is separated from the electrode by a cavity between the membrane and the electrode. The vias electrically connect the electrode to a substrate disposed on an opposite side of the electrode from a side facing the membrane. The vias are disposed in the ultrasound transducer device such that greater than 50% of the vias overlap with the cavity in a plan view.

An ultrasound transducer device includes an electrode, a membrane, and vias. The membrane is separated from the electrode by a cavity between the membrane and the electrode. The vias electrically connect the electrode to a substrate disposed on an opposite side of the electrode from a side facing the membrane. The vias are disposed in the ultrasound transducer device such that greater than 50% of the vias overlap with the cavity in a plan view.