A method includes forming a front-end-of-the-line (FEOL) element over a substrate; forming a back-end-of-the-line (BEOL) element over the FEOL element; forming an interconnection structure over the substrate; forming a conductive shielding layer electrically connected to the interconnection structure and vertically overlapping the FEOL element and the BEOL element, wherein the conductive shielding layer is grounded to the substrate through the interconnection structure; and forming a dielectric layer covering the conductive shielding layer.

In an embodiment a method for forming a pressure sensor device includes providing a pressure sensor on a substrate body, the pressure sensor comprising a membrane, depositing a top layer on top of the substrate body and the pressure sensor, connecting a cap body with the top layer, a mass of the cap body being approximately equal to a mass of the substrate body and introducing at least one opening in the cap body.

A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.

A MEMS device and a manufacturing method thereof. The manufacturing method comprises: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module. Forming the MEMS module comprises: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole.

Various embodiments of the present disclosure are directed towards a method for manufacturing an integrated chip, the method comprises forming an interconnect structure over a semiconductor substrate. An upper dielectric layer is formed over the interconnect structure. An outgas layer is formed within the upper dielectric layer. The outgas layer comprises a first material that is amorphous. A microelectromechanical systems (MEMS) substrate is formed over the interconnect structure. The MEMS substrate comprises a moveable structure directly over the outgas layer.

Ultrasonic sensing approaches are described with integrated MEMS-CMOS implementations. Embodiments include ultrasonic sensor arrays for which PMUT structures of individual detector elements are at least partially integrated into the CMOS ASIC wafer. MEMS heating elements are integrated with the PMUT structures by integrating under the PMUT structures in the CMOS wafer and/or over the PMUT structures (e.g., in the protective layer). For example, embodiments can avoid wafer bonding and can reduce other post processing involved with conventional manufacturing of PMUT ultrasonic sensors, while also improving thermal response.

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

In a microelectromechanical component according to the invention, at least one microelectromechanical element (5), electrical contacting elements (3) and an insulation layer (2.2) and thereon a sacrificial layer (2.1) formed with silicon dioxide are formed on a surface of a CMOS circuit substrate (1) and the microelectromechanical element (5) is arranged freely movably in at least a degree of freedom. At the outer edge of the microelectromechanical component, extending radially around all the elements of the CMOS circuit, a gas- and/or fluid-tight closed layer (4) which is resistant to hydrofluoric acid and is formed with silicon, germanium or aluminum oxide is formed on the surface of the CMOS circuit substrate (1).

Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.

A method includes obtaining an active device layer. The active device layer has a first surface with one or more active feature areas. First portions of the active feature areas are exposed, and second portions of the active feature areas are covered by an insulating layer. A conformal overcoat layer is formed on the first surface. A base of a microelectromechanical systems (MEMS) device layer is formed on the conformal overcoat layer. The MEMS device layer is spatially segregated from the active feature areas by removing portions of the base of the MEMS device layer in one or more antiparasitic regions (APRs) that correspond to the active feature areas. Metal MEMS features are formed on the base of the MEMS device layer. Selected portions of the active feature areas are exposed removing portions of the conformal overcoat layer that overlay the active feature areas.