Device and method of forming a device are disclosed. The device includes a substrate with a transistor component disposed in a transistor region and a micro-electrical mechanical system (MEMS) component disposed on a membrane over a lower sensor cavity in a hybrid region. The MEMS component serves as thermoelectric-based infrared sensor, a thermopile line structure which includes an absorber layer disposed over a portion of oppositely doped first and second line segments. A back-end-of-line (BEOL) dielectric is disposed on the substrate having a plurality of inter layer dielectric (ILD) layers with metal and via levels. The ILD layers include metal lines and via contacts for interconnecting the components of the device. The metal lines in the metal levels are configured to define a BEOL or an upper sensor cavity over the lower sensor cavity, and metal lines of a first metal level of the BEOL dielectric are configured to define a geometry of the MEMS component.

Device and method of forming a device are disclosed. The device includes a substrate with a transistor component disposed in a transistor region and a micro-electrical mechanical system (MEMS) component disposed on a membrane over a lower sensor cavity in a hybrid region. The MEMS component serves as thermoelectric-based infrared sensor, a thermopile line structure which includes an absorber layer disposed over a portion of oppositely doped first and second line segments. A back-end-of-line (BEOL) dielectric is disposed on the substrate having a plurality of inter layer dielectric (ILD) layers with metal and via levels. The ILD layers include metal lines and via contacts for interconnecting the components of the device. The metal lines in the metal levels are configured to define a BEOL or an upper sensor cavity over the lower sensor cavity, and metal lines of a first metal level of the BEOL dielectric are configured to define a geometry of the MEMS component.

A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers.

A semiconductor process including the following steps is provided. A wafer is provided. The wafer has a front side and a back side. The wafer has a semiconductor device on the front side. A protection layer is formed on the front side of the wafer. The protection layer covers the semiconductor device. A material of the protection layer includes a photoresist material. A surface hardening treatment process is performed on the protection layer. A first patterning process is performed on the back side of the wafer. The semiconductor process can effectively protect the front side of the wafer during a backside process.

A system for molecular mapping includes a semiconductor substrate defining a reservoir to receive a sample of molecules and a nanofluidic channel in fluid communication with the reservoir. The system also includes a plurality of electrodes, in electrical communication with the nanofluidic channel, to electrophoretically trap the sample of molecules in the nanofluidic channel. At least one avalanche photodiode is fabricated in the semiconductor substrate and disposed within an optical near-field of the nanofluidic channel to detect fluorescence emission from at least one molecule in the sample of molecules.

A method of fabricating an integrated structure for MEMS device and semiconductor device comprises steps of: providing a substrate having a transistor thereon in a semiconductor device region and a first MEMS component thereon in a MEMS region; performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers; forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in a etch stopping device region; forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and performing an etching process to remove the third dielectric layers in the MEMS region.

An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity through a via formed into the membrane layer.

A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal lines located in a first metal layer, a second plurality of metal lines located in a second metal layer, a third plurality of metal lines located in a third metal layer a plurality of edge cells, a plurality of well strap cells, and a plurality of jumper structures. Each jumper structure comprises first, second, and third metal landing pads located in the second metal layer and electrically connecting metal lines of the first and third metal layers.

Monolithic integration of microelectromechanical systems (MEMS) sensors with complementary oxide semiconductor (CMOS) electronics for pressure sensors is a very challenging task. This is primarily due to the requirement for a very high quality thin diaphragm to provide the pressure dependent MEMS deformation that can be sensed and, when seeking absolute rather than relative pressure sensors, a sealed reference cavity. Accordingly, a new manufacturing process is established based upon back-etching and bonding of a monolithic absolute silicon carbide (SiC) capacitive pressure sensor. Beneficially, the process embeds the critical features of the MEMS within a shallow trench formed within the silicon substrate and then processing the CMOS circuit. The process further benefits as it maintains that those elements of the MEMS element fabrication process that are CMOS compatible are implemented concurrently with those CMOS steps as well as the metallization steps. However, the CMOS incompatible processing is partitioned discretely.