A process for making a nanoduct includes: disposing an etchant catalyst on a semiconductor substrate including a single crystal structure; heating the semiconductor substrate to an etching temperature; introducing an oxidant; contacting the semiconductor substrate with the oxidant in a presence of the etchant catalyst; anisotropically etching the semiconductor substrate by the etchant catalyst in a presence of the oxidant in an etch direction that is coincident along a crystallographic axis of the semiconductor substrate; and forming the nanoduct as the etchant catalyst propagates along a surface of the semiconductor substrate during anisotropically etching the semiconductor substrate, the nanoduct being crystallographically aligned with the crystallographic axis of the semiconductor substrate.

A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

A process for making a nanoduct includes: disposing an etchant catalyst on a semiconductor substrate including a single crystal structure; heating the semiconductor substrate to an etching temperature; introducing an oxidant; contacting the semiconductor substrate with the oxidant in a presence of the etchant catalyst; anisotropically etching the semiconductor substrate by the etchant catalyst in a presence of the oxidant in an etch direction that is coincident along a crystallographic axis of the semiconductor substrate; and forming the nanoduct as the etchant catalyst propagates along a surface of the semiconductor substrate during anisotropically etching the semiconductor substrate, the nanoduct being crystallographically aligned with the crystallographic axis of the semiconductor substrate.

According to a method in semiconductor device fabrication, a first trench and a second trench are concurrently etched in a semi-finished semiconductor device. The first trench is a mechanical decoupling trench between a first region of an eventual semiconductor device and a second region thereof. The method further includes concurrently passivating or insulating sidewalls of the first trench and of the second trench. A related semiconductor device includes a first trench configured to provide a mechanical decoupling between a first region and a second region of the semiconductor device. The semiconductor device further includes a second trench and a sidewall coating at sidewalls of the first trench and the second trench. The sidewall coating at the sidewalls of the first trench and at the sidewalls of the second trench are of the same material.

According to a method in semiconductor device fabrication, a first trench and a second trench are concurrently etched in a semi-finished semiconductor device. The first trench is a mechanical decoupling trench between a first region of an eventual semiconductor device and a second region thereof. The method further includes concurrently passivating or insulating sidewalls of the first trench and of the second trench. A related semiconductor device includes a first trench configured to provide a mechanical decoupling between a first region and a second region of the semiconductor device. The semiconductor device further includes a second trench and a sidewall coating at sidewalls of the first trench and the second trench. The sidewall coating at the sidewalls of the first trench and at the sidewalls of the second trench are of the same material.

A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

Interfacial convective assembly can assemble any type of nanoparticles or other nanoelements in minutes to form microscale and nanoscale patterns in vias or trenches in patterned substrates. A solvent film is deposited on a patterned substrate. An aqueous suspension of nanoparticles is deposited onto the solvent film, thereby forming an interfacial liquid system comprising the nanoparticles within an enclosed space on the substrate. The substrate is then heated, thereby inducing convective flow in the interfacial liquid system. The convective flow includes solutal Marangoni convective flow in a direction towards the patterned substrate, causing nanoelements to be transferred to and bind to the patterned substrate. The nanoelements can be assembled on both hydrophilic and hydrophobic surfaces. Nanoparticles can fuse during the process to provide solid or single crystalline electrical circuit components.

A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.

The present disclosure relates to a method of manufacturing a layered structure for a MEMS apparatus, a layered structure manufactured by the method, and a MEMS apparatus 200 (300, 400, 500) comprising the layered structure. For the layered structure, a high-temperature curing step is provided in the manufacturing process, for example, after structuring the functional layer 3. The structured regions and trenches of the functional layer 3 and in particular the spring structure formed in the functional layer 3 have smoothened side walls and/or rounded corners in regions 3a after the curing step, so that their fracture limits can thus be increased and early fractures of the functional layer 3 during operation of the MEMS apparatus 200 (300, 400, 500) can be avoided.