The present techniques relate to various aspects of forming and filling high-aspect ratio trench structures (e.g., trench structures having an aspect ratio of 20 or greater, including aspect ratios in the range of 20:1 up to and including 50:1 or greater) combined with trench opening widths ranging from 0.5 micron to 50 microns. By way of example, patterned substrate described herein includes a substrate, a mask layer deposited on the substrate, and a photoresist layer deposited on the mask layer. The photoresist layer is patterned to form a pattern and the mask layer is etched through the pattern to expose the substrate. The substrate is etched through the pattern to form a structure comprising a plurality of trenches having vertical sidewall. The photoresist layer remains on the mask layer during etching of the substrate.

A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement.

An example provides a method including sputtering a metal catalyst onto a substrate, exposing the substrate to a solution that reacts with the metal catalyst to form a plurality of pores in the substrate, and etching the substrate to remove the plurality of pores to form a recess in the substrate.

According to a method in semiconductor device fabrication, a first trench and a second trench are concurrently etched in a semi-finished semiconductor device. The first trench is a mechanical decoupling trench between a first region of an eventual semiconductor device and a second region thereof. The method further includes concurrently passivating or insulating sidewalls of the first trench and of the second trench. A related semiconductor device includes a first trench configured to provide a mechanical decoupling between a first region and a second region of the semiconductor device. The semiconductor device further includes a second trench and a sidewall coating at sidewalls of the first trench and the second trench. The sidewall coating at the sidewalls of the first trench and at the sidewalls of the second trench are of the same material.

A semiconductor element and method are provided such that the method includes providing a processed substrate arrangement including a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate. The method further includes release etching for generating a kerf in the metallization layer structure at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement.

Embodiments provide a MEMS (Micro Electro Mechanical System) pressure sensor comprising a semiconductor substrate, wherein the semiconductor substrate comprises a stress decoupling structure adapted to stress decouple a first portion of the semiconductor substrate from a second portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate comprises a first buried empty space, wherein the second portion of the semiconductor substrate comprises a second buried empty space, and wherein the semiconductor substrate comprises a pressure channel fluidically connecting the first buried empty space and the second buried empty space.

A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

A method of manufacturing a semiconductor device includes forming an etching mask over a semiconductor body, forming a plurality of trenches in the semiconductor body to define a plurality of protruding semiconductor portions between adjacent trenches, and forming a protection layer in contact with a semiconductor material of the protruding semiconductor portions. The method further includes performing a wet etching step to remove portions of the etching mask and, thereafter, treating the semiconductor body with a mixture of hydrofluoric acid and ethylene glycol and bringing the semiconductor material of sidewalls of the plurality of protruding semiconductor portions into contact with the mixture of hydrofluoric acid and ethylene glycol.

Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.

A method for manufacturing a micromechanical structure in the structural layer of a wafer by forming a first gap and a second gap depositing and patterning a first etching mask and a second etching mask on a horizontal face of the structural layer, etching trenches through the structural layer in the first and second unprotected areas which are not protected by the first etching mask or the second etching mask, coating at least the sidewalls of the trenches with a protective layer and removing the second etching mask at least from a second opening in the first etching mask, so that a temporarily protected area is exposed, and etching away the structural layer in the exposed temporarily protected area.