A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

An ultrasonic transducer device includes a patterned film stack disposed on first regions of a substrate, the patterned film stack including a metal electrode layer and a bottom cavity layer formed on the metal electrode layer. The ultrasonic transducer device further includes a planarized insulation layer disposed on second regions of the substrate layer, a cavity formed in a membrane support layer and a CMP stop layer, the CMP stop layer including a top layer of the patterned film stack and the membrane support layer formed over the patterned film stack and the planarized insulation layer. The ultrasonic transducer device also includes a membrane bonded to the membrane support layer. The CMP stop layer underlies portions of the membrane support layer but not the cavity.

An electroacoustic transducer includes a frame; an element movable relative to the frame, the movable element including a membrane; an internal cavity called back volume, subjected to a reference pressure and delimited by the movable element and walls belonging to the frame; in which transducer at least one of the walls delimiting the back volume includes at least one sealed cavity and in which a pressure lower than the reference pressure prevails in the at least one sealed cavity.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.

A method of forming an ultrasonic transducer device includes forming a curved membrane over a transducer cavity. A center portion of the curved membrane is closer to a bottom surface of the transducer cavity than with respect to radially outwardly disposed portions of the curved membrane.

Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device including a conductive bonding structure disposed between a substrate and a MEMS substrate. An interconnect structure overlies the substrate. The MEMS substrate overlies the interconnect structure and includes a moveable membrane. A dielectric structure is disposed between the interconnect structure and the MEMS substrate. The conductive bonding structure is sandwiched between the interconnect structure and the MEMS substrate. The conductive bonding structure is spaced laterally between sidewalls of the dielectric structure. The conductive bonding structure, the MEMS substrate, and the interconnect structure at least partially define a cavity. The moveable membrane overlies the cavity and is spaced laterally between sidewalls of the conductive bonding structure.

A substrate for sensing, a method of manufacturing the substrate, and an analyzing apparatus including the substrate are provided. The substrate for sensing includes: a support layer; a plurality of metal nanoparticle clusters arranged on the support layer; and a plurality of perforations arranged among the plurality of metal nanoparticle clusters. The plurality of metal nanoparticle clusters each comprise a plurality of metal nanoparticles stacked in a three-dimensional structure. Each of the plurality of perforations transmits incident light therethrough.

Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. Standoffs are formed on a second side of the device wafer. A first hardmask is deposited on the second side. A second hardmask is deposited on the first hardmask. A surface of the second hardmask is planarized. A photoresist is deposited on the second hardmask, wherein the photoresist includes a MEMS device pattern. The MEMS device pattern is etched into the second hardmask. The MEMS device pattern is etched into the first hardmask, wherein the etching stops before reaching the device wafer. The photoresist and the second hardmask are removed. The MEMS device pattern is further etched into the first hardmask, wherein the further etching reaches the device wafer. The MEMS device pattern is etched into the device wafer. The first hardmask is removed.

The disclosure relates to a method for manufacturing a planarized etch-stop layer, ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method includes providing a first planarized layer on top of a surface of a substrate, the first planarized layer having a patterned and structured metallic material and a filling material. The method further includes comprises depositing on top of the first planarized layer the planarized ESL of an ESL material with low HF etch rate, wherein the planarized ESL has a low surface roughness and a thickness of less than 150 nm, in particular of less than 100 nm.