A method of making a portion of a microfluidic channel includes lithographically patterning a first pattern into a first layer of photoresist disposed on a substrate, the first pattern representative of morphology of a reservoir rock; etching the first pattern into the substrate to form a patterned substrate; disposing a second layer of photoresist onto the patterned substrate; lithographically patterning a second pattern into the second layer of photoresist to reveal portions of the patterned substrate; and depositing calcite onto the exposed portions of the patterned substrate.

A method for fabricating a microfluidic device includes providing an assembly that includes a first silicon substrate having a hydrophilic silicon oxide top surface that includes a microfluidic channel and a second silicon substrate having a hydrophilic silicon oxide bottom surface directly bonded on the top surface of the first silicon substrate, the second silicon substrate including fluidic access holes giving fluidic access to the microfluidic channel. The method also includes exposing the assembly to oxidative species including one or more oxygen atoms and to heat so as to form silicon oxide at a surface of the access holes and of the microfluidic channel.

An integrated package method for MEMS element and ASIC chip includes forming a re-layout layer on a front surface of an ASIC wafer; coating an organic compound layer on the re-layout layer and applying a lithography process to the organic compound layer to from a microcavity array; aligning and bonding an electrode connection pad layer on a front surface of an MEMS element with the microcavity array to form a closed cavity structure; thinning and exposing a silicon substrate on a back surface of the MEMS element to a desired thickness; applying the lithographic process on the MEMS element to expose the electrode connection pad layer and an electrical contact area of the re-layout layer; and manufacturing a metal connection member connected to the electrode connection pad layer and the electrical contact area. An integrated package structure for MEMS element and ASIC chip is also provided.

The disclosure describes a soft-matter electronic device having micron-scale features, and methods to fabricate the electronic device. In some embodiments, the device comprises an elastomer mold having microchannels, which are filled with an eutectic alloy to create an electrically conductive element. The microchannels are sealed with a polymer to prevent the alloy from escaping the microchannels. In some embodiments, the alloy is drawn into the microchannels using a micro-transfer printing technique. Additionally, the molds can be created using soft-lithography or other fabrication techniques. The method described herein allows creation of micron-scale circuit features with a line width and spacing that is an order-of-magnitude smaller than those previously demonstrated.

Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.

In accordance with the disclosure, a method of forming a nanochannel is provided. The method includes depositing a photosensitive film stack over a substrate; forming a pattern on the film stack using interferometric lithography; depositing a plurality of silica nanoparticles to form a structure over the pattern; removing the pattern while retaining the structure formed by the plurality of silica nanoparticles, wherein the structure comprises one or more enclosed nanochannels, wherein each of the one or more nanochannels comprise one or more sidewalls and a roof; and partially sealing the roof of one or more nanochannels, wherein the roof comprises no more than one unsealed nanochannel per squared micron.

The disclosure describes a soft-matter electronic device having micron-scale features, and methods to fabricate the electronic device. In some embodiments, the device comprises an elastomer mold having microchannels, which are filled with an eutectic alloy to create an electrically conductive element. The microchannels are sealed with a polymer to prevent the alloy from escaping the microchannels. In some embodiments, the alloy is drawn into the microchannels using a micro-transfer printing technique. Additionally, the molds can be created using soft-lithography or other fabrication techniques. The method described herein allows creation of micron-scale circuit features with a line width and spacing that is an order-of-magnitude smaller than those previously demonstrated.

A method of making a portion of a microfluidic channel includes lithographically patterning a first pattern into a first layer of photoresist disposed on a substrate, the first pattern representative of morphology of a reservoir rock; etching the first pattern into the substrate to form a patterned substrate; disposing a second layer of photoresist onto the patterned substrate; lithographically patterning a second pattern into the second layer of photoresist to reveal portions of the patterned substrate; and depositing calcite onto the exposed portions of the patterned substrate.

Provided is a method for producing a multi-layered microchannel device by using a photosensitive resin laminate, which is highly-defined and excellent in dimension accuracy and enables channels to be partially hydrophilized or hydrophobilized, wherein the method comprises step (i) of sequentially carrying out (i-a) forming a first photosensitive resin layer on a substrate, (i-b) light-exposing the first photosensitive resin layer, and (i-c) developing the light-exposed photosensitive layer and forming a channel pattern layer, to form a first channel pattern layer; and step (ii) of sequentially carrying out (ii-a) laminating a second photosensitive resin laminate on the first channel pattern layer formed in the step (i), (ii-b) light-exposing a photosensitive layer of the second photosensitive resin laminate, and (ii-c) developing the light-exposed photosensitive layer and forming a channel pattern layer, to form a second channel pattern layer.

An integrated package method for MEMS element and ASIC chip includes forming a re-layout layer on a front surface of an ASIC wafer; coating an organic compound layer on the re-layout layer and applying a lithography process to the organic compound layer to from a microcavity array; aligning and bonding an electrode connection pad layer on a front surface of an MEMS element with the microcavity array to form a closed cavity structure; thinning and exposing a silicon substrate on a back surface of the MEMS element to a desired thickness; applying the lithographic process on the MEMS element to expose the electrode connection pad layer and an electrical contact area of the re-layout layer; and manufacturing a metal connection member connected to the electrode connection pad layer and the electrical contact area. An integrated package structure for MEMS element and ASIC chip is also provided.