Patent classifications
B81C2201/0178
METHOD FOR MANUFACTURING A MICRO ELECTRO-MECHANICAL SYSTEM
A method of fabricating a semiconductor device, includes, in part, growing a first layer of oxide on a surface of a first semiconductor substrate, forming a layer of insulating material on the oxide layer, patterning and etching the insulating material and the first oxide layer to form a multitude of oxide-insulator structures and further to expose the surface of the semiconductor substrate, growing a second layer of oxide in the exposed surface of the semiconductor substrate, and removing the second layer of oxide thereby to form a cavity in which a MEMS device is formed. The process of growing oxide in the exposed surface of the cavity and removing this oxide may be repeated until the cavity depth reaches a predefined value. Optionally, a multitude of bump stops is formed in the cavity.
Pseudo SOI process
A method of processing a semiconductor substrate having a first conductivity type includes, in part, forming a first implant region of a second conductivity type in the semiconductor substrate where the first implant region is characterized by a first depth, forming a second implant region of the first conductivity type in the semiconductor substrate where the second implant region is characterized by a second depth smaller than the first depth, forming a porous layer within the semiconductor substrate where the porous layer is adjacent the first implant region, and growing an epitaxial layer on the semiconductor substrate thereby causing the porous layer to collapse and form a cavity.
PROCESS FOR PRODUCING AN ELECTROMECHANICAL DEVICE
The invention is a process for producing an electromechanical device including a movable portion that is able to deform with respect to a fixed portion. The process implements steps based on fabrication microtechnologies, applied to a substrate including an upper layer, an intermediate layer and a lower layer. These steps are: a) forming first apertures in the upper layer; b) forming an empty cavity in the intermediate layer, which step is referred to as a pre-release step because a central portion of the upper layer lying between the first apertures is pre-released; c) applying what is called a blocking layer to the upper layer, this layer covering the first apertures, the blocking layer and the central portion together forming a suspended microstructure above the empty cavity; d) producing a boundary trench in the suspended microstructure, so as to form, in this microstructure, a movable portion and a fixed portion, the movable portion forming a movable member of the electromechanical device.
CMUT transducer with motion-stopping structure and CMUT transducer forming method
The present disclosure relates to a CMUT transducer (200) comprising: a conductive or semiconductor substrate (201) coated with a stack of one or a plurality of dielectric layers (203, 213); a cavity (205, 215) formed in said stack; a conductive or semiconductor membrane (221) suspended above the cavity; at the bottom of the cavity, a conductive region (209) in contact with the upper surface of the substrate, said conductive region being interrupted on a portion of the upper surface of the substrate; andin the cavity, a stop structure (207) made of a dielectric material localized on or above the area of interruption of the conductive region (209).
Conductive bond structure to increase membrane sensitivity in MEMS device
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.
CONDUCTIVE BOND STRUCTURE TO INCREASE MEMBRANE SENSITIVTY IN MEMS DEVICE
Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure overlying a first substrate. A second substrate overlies the dielectric structure and comprises a movable element. A first bond structure is arranged between the dielectric structure and the second substrate. A second bond structure is arranged between the dielectric structure and the second substrate. At least a portion of the movable element is spaced laterally between sidewalls of the second bond structure. The first bond structure comprises a first material and the second bond structure comprises a second material different form the first material. A thickness of the first bond structure is less than a thickness of the second bond structure.
Sharp, vertically aligned nanowire electrode arrays, high-yield fabrication and intracellular recording
A nanowire electrode array has a plurality of vertical nanowires extending from a substrate, each of the nanowires including a core of unitary first dielectric material that also covers the substrate and is unitary with the substrate. Each core has a sharp sub-100 nm diameter tip and a wider base, electrode leads on sidewalls to the tip of the nanowire, and second dielectric covering the electrode leads. The tips in the array can penetrate individual cells in cell culture, such as a mini-brain culture. The substrate can include a window for simultaneous optical imaging and electrophysiological recording.
LOW VOLTAGE CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER (CMUT) DESIGN AND MANUFACTURING FLOW
A method for deigning a low voltage capacitive micromachined ultrasonic transducer (CMUT) is provided. The method includes starting from a base silicon wafer includes starting with a N-type Silicon Wafer and growing base oxide by patterning with a metal mask over the base oxide, patterning with a Field Oxide (FOX) Mask over a copper (Cu) or Aluminium (Al) metal (M1) layer that is deposited over the base oxide, depositing polysilicon over the entire silicon wafer and doping the polysilicon with a donor species with a concentration approaching its respective solid solubility limit and subsequently depositing titanium (Ti) over the doped polysilicon that is deposited on the entire silicon wafer and subsequently depositing a dielectric layer. The dielectric layer is standalone Silicon Dioxide or in a stack with Hafnium Oxide or alternatively in a stack with Silicon Nitride or a suitable stack of high relative permittivity materials.
ADAPTIVE CAVITY THICKNESS CONTROL FOR MICROMACHINED ULTRASONIC TRANSDUCER DEVICES
A method of forming an ultrasonic transducer device includes forming and patterning a film stack over a substrate, the film stack comprising a metal electrode layer and a chemical mechanical polishing (CMP) stop layer formed over the metal electrode layer; forming an insulation layer over the patterned film stack; planarizing the insulation layer to the CMP stop layer; measuring a remaining thickness of the CMP stop layer; and forming a membrane support layer over the patterned film stack, wherein the membrane support layer is formed at thickness dependent upon the measured remaining thickness of the CMP stop layer, such that a combined thickness of the CMP stop layer and the membrane support layer corresponds to a desired transducer cavity depth.
Curved cantilever design to reduce stress in MEMS actuator
The present disclosure relates to an integrated chip structure. The integrated chip structure includes a MEMS (microelectromechanical systems) actuator. The MEMS actuator has an anchor. A proof mass continuously wraps around the anchor in a closed loop. One or more curved cantilevers are coupled between the proof mass and a frame. The frame wraps around the proof mass. The one or more curved cantilevers include curved outer surfaces arranged directly between a sidewall of the frame and a sidewall of the proof mass, as viewed in a top-view.