A process for area selective atomic layer deposition (ALD) at the near atomic scale (sub 10 nm) is disclosed. A substrate surface is cleaned and terminated with hydrogen and a pattern written in the hydrogen terminated surface by selectively depassivating the surface using scanning tunneling microscope lithography. The depassivated regions are subjected to a halogen flux with the thus passivated regions further subjected to a functionalization process creating functionalized regions. The role of hydrogen and halogen can be inverted to invert the tone of the pattern. The substrate is then subjected to the ALD process, with growth occurring only in the non-functionalized regions. The substrate may then optionally be subjected to selective etching to remove the functionalized regions and the portions of the substrate under the functionalized regions.

Methods of selectively depositing a low-k dielectric film are described. In one or more embodiments, the methods include exposing a substrate to a blocking compound, the substrate including a first surface and a second surface, the first surface including hydrogen-terminated silicon, the blocking compound selectively depositing on the first surface to form a blocked first surface; and selectively depositing the low-k dielectric film on the second surface. Methods of forming an inner spacer layer are described. In one or more embodiments, the methods include pretreating a substrate to remove oxide from a hydrogen-terminated silicon (Si) channel of the substrate, the substrate including the hydrogen-terminated silicon channel and a silicon germanium (SiGe) surface; exposing the substrate to a blocking compound, the blocking compound selectively depositing on the hydrogen-terminated silicon (Si) channel to form a blocked silicon channel; and depositing the inner spacer layer selectively on the silicon germanium surface.

A method is provided for etching a silicon carbide accretion from one or more workpieces of a reaction chamber for the deposition of silicon carbide layers on a substrate. The method comprises the steps of: (I) providing a silicon carbide accretion on one or more workpieces of a reaction chamber of a reactor for deposition of silicon carbide; (II) executing at least one cycle of an etching process. Further provided is a reactor adapted to execute the method.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.