Apparatus and methods related to forming films on sidewalls of memory cell stacks in memory and logic devices. In one approach, a silicon wafer is held in a chamber of an atomic layer deposition (ALD) reactor. A temperature in the reactor is controlled to a first temperature (e.g., room temperature or below) where a first gas reactant that is provided into the chamber condenses and is adsorbed on the target wafer or substrate. The first reactant or precursor is partly vaporized at a second temperature in the reactor that is greater than the first temperature. A second gas reactant is provided into the chamber. The second gas reactant reacts with the adsorbed portion of the first gas reactant in its activated state. The reaction product is a film on the sidewall of a memory cell stack or logic devices. The foregoing steps are repeated to form a desired thickness of the film.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

Methods of depositing silicon-containing films by plasma-enhanced atomic layer deposition (PEALD) are described and can include one or more techniques to provide a chemical vapor deposition (CVD)-type component.

Methods for filling a recessed feature on a substrate are disclosed. The methods disclosed include depositing a flowable layer structure on the substrate and heating the flowable layer structure above the glass transition temperature of the flowable layer structure. Methods for depositing the flowable layer structure include depositing an aluminum oxide based flowable layer structure employing atomic layer deposition processes.

A method includes removing a dummy gate stack to form a trench between gate spacers, and removing a sacrificial layer contacting a semiconductor region. The sacrificial layer and the semiconductor region are in the trench. The method further includes depositing a gate dielectric into the trench and on the semiconductor region, depositing a liner on the gate dielectric, depositing a fluorine-containing layer over the liner, performing a drive-in process to drive fluorine in the fluorine-containing layer into the gate dielectric, and depositing a conductive layer over the gate dielectric.

The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.

Various embodiments of the present disclosure are directed towards an integrated chip including a switching layer over a semiconductor substrate. The switching layer comprises a first metal oxide. An upper conductive structure overlies the switching layer. The switching layer is spaced between opposing sidewalls of the upper conductive structure. A first dielectric layer is disposed along opposing sidewalls of the switching layer. The first dielectric layer comprises a second metal oxide different from the first metal oxide. A top surface of the switching layer and a top surface of the first dielectric layer directly underlie a bottom surface of the upper conductive structure.

There is provided a technique that includes: forming a film on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a precursor from a first supplier to the substrate and exhausting the precursor from an exhaust port installed opposite to the first supplier with the substrate interposed between the exhaust port and the first supplier; and (b) supplying a reactant from a second supplier to the substrate and exhausting the reactant from the exhaust port, wherein in (a), inert gas is supplied into the process chamber from a third supplier installed at a region, which is a region on a side of the exhaust port among a plurality of regions partitioned in the process chamber by a bisector perpendicular to straight line connecting the first supplier and the exhaust port in a plane view.

Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and/or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

A method for forming an insulating layer pattern includes providing a substrate including two or more different types of dielectric layer regions; selectively forming a blocking layer on the substrate to include a first region on which a blocking layer is formed and a second region on which no blocking layer is formed or the blocking layer is formed less than in the first region; selectively forming an insulating layer on the second region; and etching a portion of an upper portion of the insulating layer.