A package structure includes an embedded component circuit structure layer, a signal interconnection structure layer, a power structure layer, and an electronic component layer. The embedded component circuit structure layer includes at least one embedded component and has a first surface and a second surface opposite to each other. The signal interconnection structure layer is disposed on the first surface and is electrically connected to the embedded component circuit structure layer. The power structure layer is disposed on and electrically connected to the signal interconnection structure layer. The electronic component layer includes a plurality of electronic components, is disposed on the second surface, and is electrically connected to the embedded component circuit structure layer. A coefficient of thermal expansion of the signal interconnection structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power structure layer.

The semiconductor package includes a lower package including a lower package substrate and a lower semiconductor device disposed on the lower package substrate, and an upper package including an upper package substrate disposed on the lower package in a first direction and an upper semiconductor device disposed on the upper package substrate, and the upper package substrate includes a wiring structure on which the upper semiconductor device is mounted, and a heat sink disposed so that at least a portion overlaps the wiring structure in at least one of the first direction and a second direction perpendicular to the first direction and including a heat radiation pattern, wherein the heat radiation pattern comprises an insulator and a heat radiator in a repeated alternating pattern and wherein the lower semiconductor device overlaps at least a portion of the wiring structure and the portion of the heat sink in the first direction.

Provided is a redistribution structure having reduced parasitic capacitance. The redistribution structure may include a via layer and a wiring layer disposed on the via layer in a first direction perpendicular to the via layer, the wiring layer including a metal plate and a first insulation pattern configured to penetrate the metal plate in the first direction. An outer side surface of the first insulation pattern may be exposed from a side surface of the metal plate.

A semiconductor package includes a laminate package substrate, first and second power transistor dies embedded within the laminate package substrate, a driver die embedded within the laminate package substrate, a plurality of I/O routings electrically connected with I/O terminals of the driver die, a switching signal pad electrically connected with a second load terminal of the first power transistor die and a first load terminal of the second power transistor die, and a shielding pad that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies, wherein the shielding pad is exposed from the electrically insulating layer.

A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A package device and a manufacturing method thereof are provided. The package device includes a package structure, a redistribution layer, an underfill layer, a plurality of conductive pillars, another redistribution layer, and an encapsulant. The underfill layer is disposed between the package structure and the redistribution layer, and the conductive pillars and the package structure are disposed side by side between the redistribution layers. The encapsulant is disposed between the redistribution layers and surrounds the package structure and the conductive pillars.

A package structure is provided. The package structure includes a substrate including a cavity and a plurality of thermal vias connecting a bottom surface of the cavity to a bottom surface of the substrate. The package structure also includes an electronic device disposed in the cavity and thermally coupled to the plurality of thermal vias. The package structure further includes a plurality of conductive connectors formed over the electronic device and vertically overlapping the plurality of thermal vias. The package structure also includes an encapsulating material extending from top surfaces of the plurality of conductive connectors to the bottom surface of the cavity. The package structure further includes an insulating layer formed over the encapsulating material and including a redistribution layer structure electrically connected to the electronic device through the plurality of conductive connectors.

Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.

An integrated circuit chip includes; a package substrate including a first signal ball, a first semiconductor chip on the package substrate, a second semiconductor chip on the first semiconductor chip, a first bump disposed between the package substrate and the first semiconductor chip and electrically connected to the first signal ball, and a second bump disposed between the first semiconductor chip and the second semiconductor chip and electrically connected to the first signal ball, wherein during a first mode, the first signal ball receives a signal from the first semiconductor chip through the first bump and receives a signal from the second semiconductor chip through the second bump.