A package substrate according to the present disclosure includes a package substrate, an interposer disposed over the package substrate, a photonic die disposed over the interposer, a memory structure disposed over the interposer and including a controller die, a system die disposed over the interposer and partially overlapping with the photonic die and the controller die, and a lid covering the system die, the memory structure, and photonic die. The system die includes micro bumps extending from a bottom surface of the system die to a top surface of the controller die.

According to the present disclosure, upper and lower substrates may be electrically connected to a lead frame, such that wire bonding may be excluded, and electrical connection and heat dissipation may be performed without a spacer by improving a connection structure in the upper and lower substrates. In addition, a power module is introduced in which because a spacer for forming a large current path may be excluded, a current path may be shortened, such that power performance may be improved, an internal space may be additionally provided, costs may be reduced, and an overall size of the power module may be reduced.

Disclosed are embodiments of a semiconductor package. The semiconductor package may include: a first substrate; a chip stack on the first substrate, wherein the chip stack comprises one or more semiconductor chips that are stacked to be inclined at a first angle relative to a top surface of the first substrate; a tilt support structure, wherein the tilt support structure is between a first portion of the chip stack and the first substrate; and an anti-slip structure in contact with an end portion of the chip stack.

A semiconductor package includes a redistribution layer (RDL) including a redistribution wiring structure, a first semiconductor chip on the RDL and electrically connected to the redistribution wiring structure, a heat dissipation member in contact with an upper surface of the first semiconductor chip, a conductive post on the RDL and spaced apart from the first semiconductor chip in a horizontal direction, the conductive post being electrically connected to the redistribution wiring structure, a first molding member on the RDL configured to cover at least a portion of a sidewall of the first semiconductor chip and a sidewall of the conductive post, a package substrate in contact with an upper surface of the heat dissipation member and electrically connected to the conductive post, a second semiconductor chip on and electrically connected to the package substrate, and a second molding member on the package substrate and configured to cover the second semiconductor chip.

Provided is a three-dimensional integrated circuit. The three-dimensional integrated circuit includes: a first die having a first surface and a second surface opposite each other; and a second die vertically stacked on the first surface of the first die. The first die includes: a functional block arranged on the first surface of the first die; and a plurality of conductive terminals arranged on the functional block and electrically connecting the first die to the second die. The plurality of conductive terminals include a plurality of edge conductive terminals arranged on an edge region of the functional block, and the plurality of edge conductive terminals are each spaced apart from a boundary of the functional block by a first distance that is greater than or equal to a minimum distance between the plurality of conductive terminals.

A semiconductor package comprising: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip disposed on the interposer; a heat dissipation device disposed on the first semiconductor chip; and a plurality of cooling patches disposed between the heat dissipation device and the first semiconductor chip. The plurality of cooling patches directly contact the first semiconductor chip, and the plurality of cooling patches directly contact the heat dissipation device.

In the present disclosure, a central substrate is additionally disposed between an upper and lower substrates, thereby simplifying a current loop of a module. In addition, by simplifying the current loop between the upper and lower substrates, the central substrate enhances current overlap effect. Further disclosed is a power module in which an insulating pattern and a via spacer to form the current loop are reduced in size, resulting in a reduction of the overall module size.

A semiconductor package may include a base chip, at least one chip stack module on the base chip, and a sealant on the base chip and sealing the at least one chip stack module. The at least one chip stack module may have an integral structure, in which a plurality of memory chips may be stacked and uniform. Each chip stack module of the at least one chip stack module may be on the base chip while having the integral structure.

A method for forming an interconnect device. The method comprises: forming an insulating frame, wherein the insulating frame comprises: a top insulating layer formed uppermost of the insulating frame; a bottom insulating layer formed lowermost of the insulating frame; and a central insulating layer that includes a plurality of insulators disposed between the top insulating layer and the bottom insulating layer; and forming a plurality of bridge conductors extending between a first lateral surface and a second lateral surface of the central insulating layer.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.