A semiconductor device includes: a substrate including (i) a first active region comprising a plurality of unit cells, and (ii) a peripheral area surrounding at least a portion of the first active region; a gate frame comprising (i) a first portion in a wiring region and extending along a first direction, (ii) a second portion extending from one side of the first portion along a second direction crossing the first direction and connected to a first end of at least a portion among the plurality of unit cells, and (iii) a third portion extending from the first side along the second direction and connected to a second end of at least a portion among the plurality of unit cells; a first gate runner on the first portion of the gate frame and the second portion of the gate frame; and a second gate runner on the third portion.

The first semiconductor layer includes a first region positioned between field plate electrodes adjacent to each other in the first direction, a second region positioned between field plate electrodes adjacent to each other in the second direction, and a third region positioned between field plate electrodes adjacent to each other with an intersection part interposed, the intersection part being between the gate electrode extending in the first direction and the gate electrode extending in the second direction. A first-conductivity-type impurity concentration of the first region and a first-conductivity-type impurity concentration of the second region are greater than a first-conductivity-type impurity concentration of the third region.

A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.

Disclosed is a split-gate power MOS device and a manufacturing method thereof. The method comprises: forming a trench in an epitaxial layer on a substrate; forming a first insulation layer on a surface of the epitaxial layer and in the trench; filling a cavity with polycrystalline silicon, performing back-etching; performing spin-coating on the first gate conductor layer to form a second insulation layer; forming a mask on the second insulation layer, removing a portion of the first insulation layer, to expose an upper portion of the trench; forming a gate oxide layer on a sidewall of the upper portion of the trench and the surface of the epitaxial layer; and forming a second gate conductor layer in the upper portion of the trench. According to the present disclosure, voltage withstand and electric leakage between the first gate conductor layer and the second gate conductor layer are reduced.

The disclosure provides dyes for marking hydrocarbon compositions. More particularly, the disclosure relates to non-mutagenic dyes for marking hydrocarbon compositions.

A method of forming a semiconductor device includes forming a fin on a substrate, the fin comprising alternately stacked first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form a plurality of spaces each between adjacent two of the second semiconductor layers, implanting oxygen into the second semiconductor layers, and forming a gate structure wrapping around the second semiconductor layers.

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

A device includes a substrate, a gate structure, a source/drain region, a first silicide layer, a second silicide layer and a contact. The gate structure wraps around at least one vertical stack of nanostructure channels. The source/drain region abuts the gate structure. The first silicide layer includes a first metal component on the source/drain region. The second silicide layer includes a second metal component different than the first metal component, and is on the first silicide layer. The contact is on the second silicide layer.

An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

Aspects include a transistor having a gate region with a uniform gate length and a body contact region abutted to a conduction channel under the gate region to improve mitigation of the kink effect, and related methods. The transistor includes the conduction channel formed from a semiconductor layer. A source region and a drain region of the transistor are formed on opposite sides of the conduction channel in the semiconductor layer. A gate region is formed adjacent to the conduction channel. The gate region has a gate length and a gate width. The transistor has a body contact region having a second polarity and directly adjacent to the second side of the conduction channel creating a body interface between the body contact region and the conduction channel. The gate length is uniform throughout the entire gate width including where the body contact region is directly adjacent to the conduction channel.