The present disclosure relates to an electronic device comprising a semiconductor substrate and transistors having their gates contained in trenches extending in the semiconductor substrate, each transistor comprising a doped semiconductor well of a first conductivity type, the well being buried in the semiconductor substrate and in contact with two adjacent trenches among said trenches, a first doped semiconductor region of a second conductivity type, covering the well, in contact with the well, and in contact with the two adjacent trenches, a second doped semiconductor region of the second conductivity type more heavily doped than the first semiconductor region, extending in the first semiconductor region, and a third doped semiconductor region of the first conductivity type, more heavily doped than the well, covering the well, in contact with the first region, and extending in the semiconductor substrate in contact with the well.

A manufacturing method of a semiconductor device includes following steps. A semiconductor substrate including a first portion in a low voltage device region and a second portion in a middle voltage device region is provided. A first gate structure and a second gate structure are formed above the first portion and the second portion, respectively. An implantation process is performed for forming a first source/drain doped region in the first portion and a second source/drain doped region in the second portion concurrently. A first oxide layer and a second oxide layer are located above the first portion and the second portion during the implantation process, respectively. The first source/drain doped region is formed under the first oxide layer. The second source/drain doped region is formed under the second oxide layer. A thickness of the second oxide layer is greater than or substantially equal to that of the first oxide layer.

An integrated circuit (IC) device includes a plurality of first taps arranged in a plurality of first columns and a plurality of first rows, and a plurality of second taps arranged in a plurality of second columns and a plurality of second rows. The plurality of second taps has a type different from the plurality of first taps. Each first tap of the plurality of first taps extends continuously across multiple rows of first active regions. Each second tap of the plurality of second taps extends continuously across multiple rows of second active regions. The second active regions have a type different from the first active regions. Along a column direction of the plurality of first columns and the plurality of second columns, no first tap among the plurality of first taps overlaps any second tap among the plurality of second taps.

A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

A method of manufacturing an electronic device includes a) forming, in a semiconductor substrate first doped regions of a first type and second doped regions of a second type; b) depositing a dielectric layer on the upper surface of the substrate; c) after step b), forming first and second openings in dielectric layer to expose the first and second regions; d) implanting non-doping ions in the second regions to amorphize an upper portion of the second regions; e) after steps c) and d), filling the first and second openings with doped monocrystalline or polycrystalline silicon of the first type; and f) performing a thermal anneal of the device to recrystallize said upper portion of the second regions and generate crystal defects in a space charge region of a p-n junction formed at the interface between the vias and the second regions.

The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, a semiconductor device may include a channel portion, source/drain portions in contact with the channel portion on opposite sides of the channel portion, and a gate stack intersecting the channel portion. The channel portion includes a first part extending in a vertical direction relative to the substrate and a second part extending from the first part in a lateral direction relative to the substrate.

A method for manufacturing a semiconductor stack structure with ultra thin die includes manufacturing semiconductor wafers, wherein a stop layer structure formed by ion implantation is formed in the semiconductor substrate, and the conductive structures are formed to connect the dielectric stop layer and the redistribution layer of the semiconductor wafers. A bonding layer with conductive pillars is formed on the redistribution layer of another semiconductor wafer, and die sawing is performed to form multiple batches of dies. The bonding layers of a batch of dies is bonded to the exposed dielectric stop layers of the semiconductor wafers by hybrid bonding. An encapsulant covers the batch of dies, and part of the encapsulant, part of the semiconductor substrate and part of the stop layer structure of each die are removed to expose the dielectric stop layer and conductive structures of this batch of dies for bonding next batch of dies.

An apparatus is provided. The apparatus includes a disk configured to rotate during an ion implantation process. The apparatus includes a wafer support assembly coupled to the disk and configured to support one or more semiconductor wafers. The rotation of the disk causes the one or more semiconductor wafers to revolve along a path. The apparatus includes an ion implanter configured to emit an ion beam to a beam position along the path. The apparatus includes a vibration calibration device including a calibration base coupled to the disk and a first calibration unit coupled to the calibration base. The vibration calibration device is configured to move the first calibration unit from a first position to a second position to reduce a vibration associated with the apparatus.

Semiconductor devices and methods are provided. An exemplary method includes forming a first fin and a second fin, each of the first fin and the second fin comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, forming a first gate stack and a second gate stack over the first fin and the second fin, respectively, the first gate stack and the second gate stack having different gate lengths, forming a first source/drain feature adjacent to the first gate stack and a second source/drain feature adjacent to the second gate stack, after forming the second source/drain feature, performing an ion implantation process to increase a dopant concentration of an upper portion of the second source/drain feature.

Provided is an amorphous silicon thin-film transistor including an amorphous silicon semiconductor layer, a source electrode, and a drain electrode that are successively disposed on a base substrate. Ions doped by an ion implantation process are present in a region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer. A concentration of the ions in a surface region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer is greater than or equal to 5*10{circumflex over ()}20 atoms/cc.