In a mesa region sandwiched between adjacent active trenches among mesa regions that are regions each sandwiched between adjacent trenches, a third semiconductor layer has regions discretely arranged in a first direction so as to be in contact with one active trench of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction so as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched between the adjacent active trenches, a fourth semiconductor layer is disposed between the third semiconductor layer on the side in contact with the one active trench and the third semiconductor layer on the side in contact with the other active trench in plan view and between the respective regions of the third semiconductor layer discrete in the first direction.

Disclosed are a semiconductor device based on seedless silicon (Si) source/drain contact resistance reduction and laser process technology and a method of fabricating the same. The semiconductor device includes an activated seedless Si layer formed on a substrate and at least one electrode formed on the seedless Si layer, and the seedless Si layer is crystalized through a first laser process and then activated through a second laser process.

A transistor device includes a substrate, a source region provided on the substrate, a drain region in the substrate, spaced apart from the source region in a direction parallel to a top surface of the substrate, a gate electrode provided on the substrate and between the source region and the drain region, a gate insulating film interposed between the gate electrode and the substrate, and a constant current generating layer extending between the source region and the drain region, in the direction parallel to the top surface of the substrate, wherein the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

A transistor includes: a substrate; a constant current formation layer provided on the substrate; a pair of source/drain patterns provided on the constant current formation layer; a gate electrode provided between the pair of source/drain patterns; a channel pattern extending in a direction between the pair of source/drain patterns; and a gate insulating layer surrounding the channel pattern, wherein the channel pattern penetrates the gate insulating layer and the gate electrode and is electrically connected to the source pattern and the drain pattern, the gate insulating layer separates the channel pattern and the gate electrode from each other, the constant current formation layer generates a constant current between the drain pattern and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

A semiconductor structure includes a substrate, at least one first fin protruded from the substrate, and a 3D capacitor disposed over the substrate. The 3D capacitor includes a doped electrode conformally disposed in the first fin, a metal electrode disposed over the doped electrode, and a dielectric layer disposed between the doped electrode and the metal electrode.

A bipolar transistor includes a sub-collector doped with a first dopant type and situated in a semiconductor substrate, a device layer doped with the first dopant type situated over the sub-collector, and a shallow trench isolation (STI) situated in the device layer and bordering a collector of the bipolar transistor. The bipolar transistor further includes a Reduced Surface Layer (RESURF) region doped with a second dopant type opposite the first dopant type situated between the collector and the STI, wherein the RESURF region protects against breakdown of the bipolar transistor.

A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.

Methods of processing a substrate are disclosed herein which include treating a surface of a first portion of the substrate to produce a treated substrate having a treated first portion and a second portion, wherein a bonding speed of the treated first portion to another substrate is different than a bonding speed of the second portion to the other substrate. A method of bonding a first substrate to a second substrate is also disclosed.