There is provided a semiconductor memory device that has improved performance and/or reliability. The semiconductor memory device includes a substrate, a stacked structure including a plurality of gate electrodes stacked on the substrate and spaced apart from each other in a first direction, the first direction being perpendicular to an upper surface of the substrate, a channel structure extending in the first direction and crossing the plurality of gate electrodes, and a dam structure extending in the first direction and surrounding at least a portion of the stacked structure in a plan view, on the substrate. A height of an upper surface of the dam structure from the upper surface of the substrate is lower than a height of the channel structure from the upper surface of the substrate.

An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.

A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

A semiconductor device includes an insulated circuit board having a lower surface, a heat dissipation base plate having a front surface that includes an arrangement region in which the lower surface of the insulated circuit board is arranged via solder and a solder region in which the solder spreads over the arrangement region, a plating film formed on the front surface of the heat dissipation base plate except for the solder region, and an alloy layer disposed between the solder and the heat dissipation base plate in the arrangement region. The alloy layer contains a solder component that is contained in the solder. In particular, in the semiconductor device, the plating film is formed on an entire surface of the heat dissipation base plate except for an opening region surrounding an outer periphery of the arrangement region where the insulated circuit board is arranged via the solder.

A fan-out wafer-level packaging (FOWLP) unit including a substrate, at least one first die, a first dielectric layer, a plurality of first conductive circuits, a second dielectric layer, a plurality of second conductive circuits, and at least one second die is provided. A range perpendicular to a second surface of the first die is defined as a chip area. The second dielectric layer is provided with a plurality of second slots allowing the second conductive circuit to expose and form bonding pads. The bonding pads located around the chip area are first bonding pads. The second die is disposed over the second dielectric layer by flip chip and electrically connected to the first die which is electrically connected with the outside by the first bonding pads. Thereby problems of conventional FOWLP generated during manufacturing of the conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

A system comprises: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power switch including a drain terminal, a source terminal, and a gate terminal; and a controller configured to detect a change in current at the source terminal of the power switch using a complex impedance of a metal trace connected to the source terminal of the power switch, and control a gate control signal to the gate terminal based on the detected change in current.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

A semiconductor packaging device includes a packaging module, a heat dissipation cover and a thermal interface material layer. The package module includes a substrate, and a working chip mounted on the substrate. The heat dissipation cover includes a metal cover fixed on the substrate and covering the working chip, an accommodating recess located on the metal cover to accommodate the working chip, and a plurality of protrusive columns respectively formed on the metal cover and distributed within the accommodating recess at intervals. The depth of the accommodating recess is greater than the height of each protrusive column, and the accommodating recess is greater than the working chip. The thermal interface material layer is non-solid, and located within the accommodating recess between the protrusive columns to wrap the protrusive columns and contact with the working chip, the metal cover and the protrusive columns.