Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

The semiconductor structure includes a die structure including: a substrate, a first dielectric disposed over the substrate, a first interconnect structure disposed within the first dielectric, a second dielectric disposed on the first dielectric, and a conductive pad surrounded by the second dielectric; a capping member surrounding the die structure; and an insulating member surrounding the capping member, wherein the capping member includes a first oxynitride layer in contact with the die structure or the insulating member.

According to some embodiments, a semiconductor package may include a first semiconductor chip; a second semiconductor chip disposed on a first semiconductor chip; a wall structure disposed on the first semiconductor chip and spaced apart from the second semiconductor chip in a first direction; and a mold layer covering the first and second semiconductor chips, wherein the first semiconductor chip includes a transceiver disposed thereon and spaced apart from the second semiconductor chip, the mold layer has an opening exposing the transceiver, the wall structure is disposed in the opening and is in contact with an inner wall of the mold layer exposed to the opening, the mold layer has a first height, and the wall structure has a second height smaller than the first height.

A display module includes: a substrate having a mounting surface, four side surfaces, and a rear surface opposite to the mounting surface, the substrate including a thin film transistor layer (TFT) provided on the mounting surface; a plurality of inorganic light-emitting diodes provided on the mounting surface of the substrate; a side wiring electrically connected to the TFT layer and extending along a first pair of side surfaces among the four side surfaces of the substrate; a front cover covering the TFT layer and the plurality of inorganic light emitting devices in a first direction; a metal plate provided on the rear surface of the substrate; a side cover covering the side wiring and the four side surfaces; and a side member provided on a side of the side cover and grounded to the metal plate, wherein the side member is provided on a first side surface of the first pair of side surfaces along which the side wiring extends among the four side surfaces.

A method of manufacturing a display device includes forming a thin film transistor layer in an active area of a substrate, forming a metal layer on an edge area of the substrate, transferring first coating patterns to the edge area, the first coating patterns covering a portion of the metal layer corresponding to shapes of side surface lines, etching the metal layer to form the side surface lines, an upper surface of each of the side surface lines being covered by the first coating patterns, transferring a second coating pattern to the edge area, the second coating pattern covering a side surface of each of the side surface lines and the first coating patterns, and transferring light emitting elements to the thin film transistor layer. The second coating pattern includes openings corresponding to the first coating patterns in a plan view.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface with conductive contacts, in a first layer; a first material surrounding the first die and extending along a thickness of the first die from the second surface, and wherein the first material includes first particles having an average diameter between 200 and 500 nanometers; a second material surrounding the first die and extending along the thickness of the first die from the first surface, and wherein the second material includes second particles having an average diameter between 0.5 and 12 microns; an interface portion, between the first and second materials, including the first and second particles; and a second die, in a second layer on the first layer, electrically coupled to the conductive contacts on the first die.

A method of fabricating a semiconductor device includes providing a GaN substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate, the heterojunction supporting a 2-dimensional electron gas (2DEG) channel in the GaN substrate. A composite surface passivation layer is formed over a top surface of the epitaxial layer, wherein the composite surface passivation layer comprises a first passivation layer portion formed proximate to a first region of the GaN device and a second passivation layer portion formed proximate to a second region of the GaN device. The first and second passivation layer portions are disposed laterally adjacent to each other over the epitaxial layer, wherein the first passivation layer portion is formed in a first process and the second passivation layer portion is formed in a second process.

A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; and an insulating layer. The gate electrode includes a junction portion and a drain-side protruding portion. The insulating layer includes an in-situ Si.sub.3N.sub.4 film and an ex-situ Si.sub.3N.sub.4 film. At least one of the following is satisfied: (a) the halogen concentration of the in-situ Si.sub.3N.sub.4 film is lower than the halogen concentration of the ex-situ Si.sub.3N.sub.4 film; or (b) the interface oxygen concentration between the in-situ Si.sub.3N.sub.4 film and the nitride semiconductor layer is lower than the interface oxygen concentration between the ex-situ Si.sub.3N.sub.4 film and the in-situ Si.sub.3N.sub.4 film.

A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; a drain-side insulating layer; and a source-side insulating layer. The gate electrode includes a junction portion, a drain-side protruding portion, and a source-side protruding portion. The protrusion length of the source-side protruding portion is longer than the protrusion length of the drain-side protruding portion. The bottom surface of the source-side protruding portion includes a step. The height of an end portion of the bottom surface of the source-side protruding portion is greater than the height of an end portion of the bottom surface of the drain-side protruding portion.