A semiconductor device includes a drift region, an active region in the drift region, and an edge termination region in the drift region adjacent to the active region. The edge termination region includes one or more guard rings in the drift region. The drift region has a first conductivity type and the one or more guard rings have a second conductivity type. The edge termination region may also include a passivation layer that is disposed on the one or more guard rings and on the drift region in the edge termination region. The passivation layer has a first thickness over each guard ring and a second thickness over the drift region, where the first thickness is greater than the second thickness. Alternatively, the edge termination region may also include a passivation layer that is only disposed on the one or more guard rings in the edge termination region.

A semiconductor wafer includes a semiconductor substrate on which an interlayer insulating film and a surface protective film are laminated on an upper surface. A plurality of semiconductor elements to be divided into small pieces by dicing along an opening formed in the surface protective film are formed on the semiconductor substrate. An end of the interlayer insulating film is retracted more than an end of the surface protective film with respect to an end of the semiconductor substrate to be formed by the dicing, and a shape of the end of the interlayer insulating film is set such that, in each of the semiconductor elements after the dicing, a distance Lx from a corner of the semiconductor substrate to be formed by the dicing to the end of the interlayer insulating film and a thickness d of the semiconductor substrate satisfy a certain condition.

Semiconductor devices including dual surface passivation layers are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, a drain access region, and a source access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate electrode is disposed in the gate region of the semiconductor substrate, where the gate electrode includes an asymmetrical source-side field plate (e.g., including a single-step profile) extending over at least a portion of the source access region of the semiconductor substrate.

A nitride-based semiconductor circuit including a first semiconductor substrate, a second semiconductor substrate, a nitride-based heterostructure, connectors, a first patterned conductive layer, a second patterned conductive layer, and connecting vias is provided. The second substrate is disposed on the first substrate. The first substrate has first dopants, and the second substrate has second dopants, which is different from the first dopants, and a pn junction is formed between the first substrate and the second substrate. The nitride-based heterostructure is disposed on the second substrate. The connectors are disposed on the nitride-based heterostructure. The first and second patterned conductive layers are disposed on the connectors. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first substrate to one of the connectors. The second interconnection electrically connects the second substrate to another one of the connectors.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

A power semiconductor device includes a semiconductor structure comprising an active region, an encapsulation material on the semiconductor structure, and a plurality of adhesion features in or on the semiconductor structure along an interface with the encapsulation material. The interface is laterally between the active region and at least one edge of the semiconductor structure. Related devices and fabrication methods are also discussed.

The present invention relates to a semiconductor device including: a semiconductor substrate having: an active region through which a main current flows; and a termination region around the active region; a polyimide film disposed in the active region and the termination region; and a passivation film disposed as a film underlying the polyimide film, wherein the termination region includes, in order from a side of the active region, a breakdown voltage holding region and an outermost peripheral region, the polyimide film is disposed except for a dicing remaining portion of the outermost peripheral region, and the passivation film is disposed, as the underlying film, at least in a region where the polyimide film is disposed.

An integrated circuit with a first conductive region, a second conductive region, a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region, and at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type. Each dielectric layer of a first material type has a thickness in a range from 0.5 m to 5.0 m, and the at least one dielectric layer of a second material type is not contacting a metal and has a thickness less than 2.0 m, and the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.

A semiconductor packaging assembly includes a redistribution layered structure having a plurality of device regions and a plurality of cutting regions separating the device regions, a plurality of recess structures respectively formed in the cutting regions, a plurality of chips respectively disposed in the device regions, and an encapsulating layer formed on the redistribution layered structure to fill the recess structures and enclose the chips.

Embodiments of the present disclosure provide a semiconductor structure including a first metal contact, where at least a portion of the first metal contact extends vertically from a substrate to a top portion of the semiconductor structure. The first metal contact having an exposed surface at the top portion of the semiconductor structure. A dielectric cap may be configured around the first metal contact. The dielectric cap is configured to electrically separate a first area of the semiconductor structure from a second area of the semiconductor structure. The first area of the semiconductor structure includes the first metal contact.