Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

The technology of this application relates to a switching power module that includes a substrate, a die embedded in the substrate, and a packaging layer. The packaging layer covers an integrated circuit layout layer of the die. The packaging layer packages the integrated circuit layout layer of the die, the die includes a composite material layer covering the integrated circuit layout layer, and the composite material layer includes at least two material layers that have different functions. The at least two material layers include a first material layer covering the integrated circuit layout layer, the first material layer is a mixed layer of undoped silicate glass and tetraethyl orthosilicate, and the first material layer is filled in a gap between metal protrusions of the integrated circuit layout layer, thereby improving an isolation effect between the metal protrusions. The mixed layer of the undoped silicate glass and the tetraethyl orthosilicate has a good thermal stress effect.

A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.

A wafer structure comprises a semiconductor wafer having a first side opposite a second side in a longitudinal direction. The wafer structure also comprises active circuitry formed on the first side of the semiconductor wafer. The active circuitry demarcates a voltage boundary between a first voltage zone and a second voltage zone in the semiconductor wafer. The wafer structure further includes an insulation layer including an insulation coating and an insulation barrier. The insulation coating is formed on the second side of the semiconductor wafer and extends to an insulation surface in the longitudinal direction. The insulation barrier extends from the insulation surface to the first side of the semiconductor wafer at the voltage boundary. The wafer structure yet further includes a conductive coating layer formed proximate to the insulation surface of a conductive coating material.

A high electron mobility transistor (HEMT) device including a substrate and a semiconductor stack is provided. The semiconductor stack comprises a lower channel layer, an insertion layer (ISL) positioned above the lower channel layer for confining electrons in the lower channel layer, an upper channel layer, an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer, and a barrier layer positioned above the IEL. The ISL and the IEL are formed above the lower channel layer and the upper channel layer respectively to create a first and second wide bandgap heterojunction. The ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer. The potential barrier prevents or reduces a flow of hot electrons.

A semiconductor device may include a semiconductor substrate, an element layer on the semiconductor substrate, a wiring layer on the element layer, and a buffer layer provided between the semiconductor substrate and the element layer or between the element layer and the wiring layer. The buffer layer may include a first buffer layer including a plurality of first voids spaced apart from each other and a second buffer layer provided on the first buffer layer. The buffer layer includes: a first buffer layer including a plurality of first voids spaced apart from each other, and a second buffer layer provided on the first buffer layer and including a plurality of second voids spaced apart from each other, The plurality of second voids are disposed at a different height level than the plurality of first voids. The plurality of second voids include a plurality of pairs of adjacent second voids. In a plan view, each of the first voids of the buffer layer is disposed between a corresponding one of the plurality of pairs of adjacent second voids.