An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A protective film forming agent that, in dicing of a semiconductor wafer, is used to form a protective film on the surface of the semiconductor wafer, can form a protective film that has excellent laser processability, and has excellent solubility of a light-absorbing agent; and a method for producing a semiconductor chip using the protective film forming agent. The protective film forming agent includes a water-soluble resin, a light-absorbing agent, a basic compound, and a solvent. The basic compound is an alkylamine, an alkanolamine, an imidazole compound, ammonia, or an alkali metal hydroxide. The light-absorbing agent content of the protective film forming agent is 0.1-10 mass % (inclusive).

This insulation module is provided with: a first conductor and a second conductor, which are buried in an insulating layer so as to face each other at a distance in the thickness direction of the insulating layer; a first electrode which is connected to the first conductor; a second electrode which is connected to the second conductor, while being arranged at a position that is away from the first electrode when viewed from the thickness direction of the insulating layer; a passivation layer which is formed on the surface of the insulating layer; a low dielectric constant layer which is formed on the surface of the passivation layer, and has a lower dielectric constant than the passivation layer; and a mold resin which covers the low dielectric constant layer.

A microelectronic circuit package may include one or more operative channels, each of the one or more operative channels containing a reactive material, and a seal covering at least a portion of the one or more operative channels. At least one of the one or more operative channels has a maximum width of less than about 100 microns. The seal is non-reactive with the reactive material. Also disclosed are methods of manufacturing a microelectronic circuit package comprising at least one operative channel containing a reactive material.

A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the top die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least 100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

An electronic component includes a covered object, an electrode that is arranged on the covered object and has an electrode side wall on the covered object, a wiring that is arranged on the covered object in a periphery of the electrode, an inorganic film with an insulating property that has an inner covering portion covering the electrode so as to expose the electrode side wall and an outer covering portion covering the wiring at an interval from the inner covering portion, and an organic film with an insulating property that extends across the inner covering portion and the outer covering portion and covers the electrode between the inner covering portion and the outer covering portion.

The semiconductor structure includes a die structure including: a substrate, a first dielectric disposed over the substrate, a first interconnect structure disposed within the first dielectric, a second dielectric disposed on the first dielectric, and a conductive pad surrounded by the second dielectric, a capping member surrounding the die structure, and an insulating member surrounding the capping member, wherein the capping member includes a first oxynitride layer in contact with the die structure or the insulating member.

An electrical device having a capacitor including: a bottom electrode; a dielectric structure extending conformally on the bottom electrode and comprising dielectric layers, wherein the dielectric structure extends only within a central region of the bottom electrode; a top electrode extending conformally on the dielectric structure; and a passivation layer extending on the bottom electrode within a peripheral region of the bottom electrode, the peripheral region surrounding the dielectric structure and extending up to lateral edges of the electrical device, and wherein: the lateral edges of each of the dielectric layers are covered at least by the passivation layer.