Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.

A workpiece cutting method includes: a first step of pasting an expandable sheet on a workpiece; a second step of irradiating, after the first step, the workpiece with laser light to form a modified region and expanding the expandable sheet to divide the workpiece into a plurality of chips, and meanwhile, to form a gap disposed between the plurality of chips and extending to a side surface of the workpiece; a third step of irradiating the expandable sheet with an ultraviolet light after the first step; a fourth step of filling, after the second step and the third step, the gap with resin from an outer edge part of the workpiece including the side surface; a fifth step of curing the resin after the fourth step; and a sixth step of taking out the chips from above the expandable sheet after the fifth step.

In one example, an electronic device comprises a substrate comprising a conductive structure and a dielectric structure, the dielectric structure comprising an upper dielectric layer, an electronic component over a top side of the substrate and coupled with the conductive structure, an encapsulant over the top side of the substrate and adjacent a lateral side of the electronic component, and a shield over the top side of the electronic component and contacting a lateral side of the encapsulant and a first lateral side of the substrate. The conductive structure comprises a first tab structure at the first lateral side of the substrate, and wherein the first tab structure contacts the shield and extends above the upper dielectric layer. Other examples and related methods are also disclosed herein.

In one example, a semiconductor structure or device comprises a substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure, an electronic component on the top side of the conductive structure, a package body on the top side of the conductive structure and contacting a side of the electronic component, a shield on a top side of the package body and a lateral side of the package body, and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.

A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

A semiconductor device assembly can include a first semiconductor device comprising CMOS circuitry at a first active surface and a second semiconductor device having a footprint smaller than that of the first semiconductor device and including memory array circuitry at a second active surface hybrid-bonded to the first active surface. The assembly can further include a gapfill material directly contacting the first active surface of the first semiconductor device and having an upper surface coplanar with a back surface of the second semiconductor device, and a metallization layer disposed over the second semiconductor device and the gapfill material. The metallization layer can include conductive structures operably coupled to the second semiconductor device through back-side contacts of the second semiconductor device. The assembly can further include a plurality of bond pads disposed at an upper surface of the metallization layer and coupled to the conductive structures of the metallization layer.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.

A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.