In one example, an electronic device, comprises a substrate comprising a dielectric structure and a conductive structure, an electronic component over a top side of the substrate, wherein the electronic component is coupled with the conductive structure; an encapsulant over the top side of the substrate and contacting a lateral side of the electronic component, wherein the encapsulant comprises a first trench on a top side of the encapsulant adjacent to the electronic component, a lid over the top side of the encapsulant and covering the electronic component; and an interface material between the top side of the encapsulant and the lid, and in the first trench. Other examples and related methods are also disclosed herein.

Provided is a method for forming a partial shielding for an electronic assembly, comprising: providing an electronic assembly mounted on a mother board, wherein the electronic assembly comprises a substrate, and at least one electronic component and a conductive pattern mounted on a top surface of the substrate; disposing a mask onto the substrate to cover the at least one electronic component; forming an encapsulant layer on the mother board to encapsulate at least the electronic assembly; forming a trench through the encapsulant layer to expose at least a portion of the conductive pattern and at least a portion of lateral surfaces of the mask; forming a shielding layer on the mother board to cover the encapsulant layer and fill in the trench; and detaching the mask from the mother board.

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

A method for manufacturing a semiconductor apparatus includes the steps of: applying a first adhesive having heat dissipation property and thermosetting property onto each of surfaces of a plurality of devices joined to a surface of a substrate, and thereafter mounting heat dissipation blocks, and performing bonding by heat treatment; applying a second adhesive having heat dissipation property and thermosetting property onto each of surfaces of the heat dissipation blocks, so as to be higher than a height A of a molding resin that seals the devices in a later step; and curing the second adhesives by heat treatment while aligning, by using thicknesses of the second adhesives, heights to surfaces of the second adhesives so that the heights are matched with the height A of the molding resin.

A power semiconductor device includes a semiconductor structure comprising an active region, an encapsulation material on the semiconductor structure, and a plurality of adhesion features in or on the semiconductor structure along an interface with the encapsulation material. The interface is laterally between the active region and at least one edge of the semiconductor structure. Related devices and fabrication methods are also discussed.

A package includes a first carrier including a component mounting area, a second carrier including at least one lead section, at least one electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the at least one electronic component, encapsulating at least part of the first carrier including encapsulating the entire sidewalls of the first carrier, and encapsulating part of the second carrier, wherein the first carrier is assembled with the second carrier so that the at least one electronic component and/or the first carrier is electrically connected with the at least one lead section, and wherein the first carrier has a first thickness and the second carrier has a second thickness being smaller than the first thickness.

A package is disclosed. In one example, the package comprises a carrier having a first main surface at which at least one first pad is formed and an opposing second main surface at which at least one second pad is formed at least partially in an electrically insulating layer structure of the carrier. An electronic component is mounted on or above the carrier, electrically connected with the at least one first pad and arranged spaced with respect to the at least one second pad by the carrier. The at least one second pad comprises a first metallic area facing the carrier and a second metallic area connected at an interface with the first metallic area and facing away from the carrier.

A semiconductor package and a method of manufacturing the same are provided. The method includes stacking plurality of semiconductor chips on a package substrate, covering the package substrate with a photoresist film to surround side and top surfaces of the plurality of semiconductor chips, exposing and developing the photoresist film to form a plurality of openings in the photoresist film over an outer region of the top surface of a corresponding semiconductor chip of the plurality of semiconductor chips, filling the plurality of openings with a conductive material to form a plurality of conductive posts, removing the photoresist film, and forming a molding member surrounding the plurality of semiconductor chips and the plurality of conductive posts, wherein the capping layer comprises a polymer material layer including sulfur.

A method of processing a metal layer for a semiconductor structure includes performing a metal surface recovery process to remove an oxidized or nitridized layer from a surface of the metal layer and recover a metal surface of the metal layer, performing a metal passivation process to passivate the metal surface of the metal layer and form a passivation layer, and performing an encapsulation layer deposition process to deposit an encapsulation layer on the passivation layer.

A method of forming an integrated circuit (IC) is provided. The method includes forming a seed layer of a first metal material over a circuit on a device side of a semiconductor die. The method also includes forming a multi-layer conductive contact on the seed layer. The multi-layer conductive contact has a width in a first dimension and includes a plurality of layers of different metal materials and a portion of the seed layer extends outwardly from a periphery of the multi-layer conductive contact. The method further includes forming a sacrificial layer of the first metal material over the multi-layer conductive contact. The method yet further includes etching to remove the seed layer and the sacrificial layer.