An electronic package and a manufacturing method thereof are provided, including a first electronic component disposed on a first side of a first substrate disposed on a first surface of a circuit board, a plurality of bonding wires formed on the first side of the first substrate for electrically connecting the first substrate to the circuit board. A second electronic component is disposed on the first surface of the circuit board for the first electronic component to be electrically connected to the second electronic component via the first substrate, the plurality of bonding wires and the circuit board in sequence. A first encapsulant is formed on the first surface of the circuit board to cover the first substrate, the first electronic component and the plurality of bonding wires. Thereby, the present disclosure can effectively reduce the size of the first substrate and the electronic package.

A semiconductor package assembly, comprising: a semiconductor package comprising: a semiconductor die mounted on a substrate; a pair of interconnection blocks mounted at opposite sides of the semiconductor die; and an encapsulant layer, wherein the pair of interconnection blocks have respective top surfaces exposed and a top surface of the semiconductor die is exposed; and an inductor block mounted on the semiconductor package, comprising: an inductor extending through the insulation body in a horizontal direction, and having a pair of inductor contact pads exposed at a bottom surface of the insulation body, wherein the pair of inductor contact pads are aligned to and electrically coupled to the pair of interconnection blocks; and a thermally conductive coating formed at an outer surface of the insulation body and extending in a vertical direction of the insulation body from the bottom surface to a top surface of the insulation body.

A semiconductor structure, including a first semiconductor structure, a second semiconductor structure, and a filling material is disclosed. The first semiconductor structure has a first surface and a second surface opposite to the first surface. The first semiconductor structure has a body portion and a semiconductor brim portion protruded from the body portion. The semiconductor brim portion is closer to the second surface. The second semiconductor structure is in contact with the first surface of the first semiconductor structure and bonded with the first semiconductor structure. The filling material surrounds the first semiconductor structure and is filled between the semiconductor brim portion and the second semiconductor structure. The filling material wraps around and covers the semiconductor brim portion, and a sidewall of the filling material is aligned with a sidewall of the second semiconductor structure.

A semiconductor package includes: a lower substrate; a semiconductor chip disposed on the lower substrate; an upper substrate disposed on the semiconductor chip, having a lower surface facing the semiconductor chip, and including step structures disposed below the lower surface; a connection structure disposed around the semiconductor chip and connecting the lower substrate to the upper substrate; and an encapsulant filling a space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure. The lower surface of the upper substrate has a first surface portion on which the step structures are disposed and a second surface portion having a step with respect to the lower surface of the step structures, and the second surface portion extends between opposite edges of the upper substrate.

A manufacturing method of a package is provided. The method includes the following steps. A wafer substrate having first bonding pads is provided. A die is placed on the wafer substrate, wherein the die comprises second bonding pads bonded to the first bonding pads. The die is encapsulated by an etch stop layer and a first encapsulant. A redistribution structure is disposed over the die, the etch stop layer and the first encapsulant. A portion of the redistribution structure is removed to expose the first encapsulant. The first encapsulant is removed to expose the etch stop layer. A dielectric structure is disposed over the exposed etch stop layer and laterally encapsulates the die and the redistribution structure.

Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.

A method including the following steps is provided. A seed layer is formed. Conductive material is formed on the seed layer by performing an electrolytic plating process with an electrolytic composition comprising: a source of copper ions; an accelerator agent; and a suppressor agent, by structure represented (1) or (2): ##STR00001##
wherein x is between 2 and 50, y is between 5 and 75, and R1 is an alkyl group of 1 to 3 carbon atoms. A portion of the seed layer exposed by the conductive material is removed.

A semiconductor device comprises a semiconductor chip and an electrically conductive chip carrier, wherein the semiconductor chip is mounted on the chip carrier. The semiconductor device furthermore comprises an electrically conductive extension element mechanically connected to the chip carrier, wherein the extension element and the chip carrier are formed as an integral single piece. A part of the chip carrier which has the extension element is configured as an antenna.

An electronic circuit module. The module has a multilayered LTCC circuit carrier made of structured inorganic substrate layers, which have electrical and/or thermal conduction structures for electrical and/or thermal conduction, at least one electronic component, which is arranged on a first side and/or an opposite second side of the LTCC circuit carrier, and at least one SiC power semiconductor. The at least one SiC power semiconductor is embedded in the multilayered LTCC circuit carrier and enclosed at least on three sides by the multilayered LTCC circuit carrier. Connection contacts of the SiC power semiconductor contact the electrical and/or thermal conduction structures of the LTCC circuit carrier.

An electronic device that includes a substrate and a die disposed on the substrate, the die having an active surface. Wire bonds are attached from the active surface of the die to the substrate. A radiation barrier is attached to the substrate and disposed over the die. The radiation barrier is configured to mitigate electromagnetic radiation exposure to the die. A mold compound is formed over the die, the wire bonds, and the radiation barrier.