Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.

A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a peripheral circuit bonded to the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; plate lines extending in the second direction; and a first dielectric layer disposed between the semiconductor body and the word line and the plate line.

The object is to provide a technology for enabling reduction in the size of a semiconductor device. The semiconductor device includes a first semiconductor element and a second semiconductor element. An output of the first semiconductor element is connected to an output of the second semiconductor element through wiring. A main current flows through the first semiconductor element, and a sensing current flows through the second semiconductor element. The sensing current has a correlation with the main current. The semiconductor device further includes a current sensor. The current sensor senses the sensing current flowing through the second semiconductor element in a contactless manner.

A semiconductor device includes a substrate including a first device region and a second device region, a first active pattern on the first device region, a second active pattern, which has a width smaller than the first active pattern, on the second device region, a first channel pattern on the first active pattern, a first source/drain pattern connected to the first channel pattern, a second channel pattern on the second active pattern, a second source/drain pattern connected to the second channel pattern, and a gate electrode that extends from the first channel pattern to the second channel pattern in a first direction. The first channel pattern includes a plurality of semiconductor patterns, which are vertically stacked and spaced apart from each other. The second channel pattern protrudes vertically from the second active pattern.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

A semiconductor device includes a substrate, a bit line on the substrate extending in a first direction parallel to an upper surface of the substrate, a first semiconductor pattern and a second semiconductor pattern on the bit line, each extending in a second direction perpendicular to the upper surface of the substrate, and spaced apart from each other in the first direction, a word line between the first semiconductor pattern and the second semiconductor pattern extending in the second direction, a first connection structure on one end portion of the first semiconductor pattern, a second connection structure on one end portion of the second semiconductor pattern, a data storage pattern on each of the first connection structure and the second connection structure, and a gap between the first connection structure and the second connection structure.

According to an aspect of the present disclosure, a semiconductor device includes a cell structure including a gate stacking structure in a first region and an insulation structure in a second region, a first wiring portion disposed on a first surface of the cell structure, a second wiring portion disposed on a second surface of the cell structure opposite to the first surface, a channel structure at least partially penetrating the gate stacking structure and being electrically coupled with the first wiring portion and the second wiring portion, and a capacitor structure including a plurality of penetration structures. The gate stacking structure includes a plurality of gate electrodes while interposing an interlayer insulation layer therebetween. Each of the plurality of penetration structures at least partially penetrates at least a portion of the insulation structure.

A semiconductor device includes a substrate, a source/drain pattern on the substrate, a gate structure on the substrate, an active contact connected to the source/drain pattern, a gate contact connected to the gate structure, and a wiring structure on the active contact, where the wiring structure includes a bridge wiring layer and a plurality of conductive wiring layers, the bridge wiring layer includes an active via connected to the active contact and a gate via connected to the gate contact, and each conductive wiring layer of the plurality of conductive wiring layers includes an active via connected to the active contact, a gate via connected to the gate contact, an active line on the active via of the respective conductive wiring layer, and a gate line on the gate via of the respective conductive wiring layer.

A semiconductor device including a semiconductor substrate, an interlayer insulation layer on the semiconductor substrate, a first via structure passing through the semiconductor substrate and the interlayer insulation layer and having a first diameter, and a second via structure passing through the semiconductor substrate and the interlayer insulation layer, the second via structure having a second diameter greater than the first diameter, at a same vertical level may be provided. A sidewall of the first via structure may include at least one undercut region horizontally protruding toward a center of the first via structure, and an outer sidewall of the second via structure may be in contact with either the semiconductor substrate or the interlayer insulation layer at an area above the undercut region.