A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.

In an output circuit of a semiconductor integrated circuit device, an output transistor part including a transistor connected between VSS and an output terminal has first and second active regions overlapping each other in planar view. A power line and an output line are placed in an interconnect layer on the back side so as to overlap the first and second active regions in planar view. The power line is connected to the lower face of the portion that is to be the source of the first active region through a via, and the output line is connected to the lower face of the portion that is to be the drain of the first active region through a via.

According to some embodiments of the inventive concepts, an integrated circuit device may be provided. The integrated circuit device may include a lower conductive line, a conductive via on the lower conductive line and a stopping pattern between the lower conductive line and the conductive via. A side surface of the stopping pattern may be aligned with the side surface of the lower conductive line and the side surface of the conductive via.

A memory device includes a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode. The bottom electrode has a first width W1. The top electrode has a top surface that has a second width W2 between two edges of the top surface. The memory cell has a first height H1 extending from a lower surface of the bottom electrode to the top surface of the top electrode. The memory device further includes a top contact wire coupled to the top electrode. The top contact wire has a top surface that has a third width W3, a second height H2 at a location between two adjacent memory cells, and a third height H3 extending between the top surface of the top contact wire and the insulating layer, where W1>W3>W2 and H2>H1>H3.

A microelectronic device comprises a vertical stack of memory cells. The vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, a conductive pillar structure in electrical communication with the vertical stack of access devices, and an isolated conductive structure in electrical communication with a multiplexer comprising a vertically uppermost access device of the vertical stack of access devices. The microelectronic device further comprises a stack structure comprising conductive structures interleaved with insulative structures, at least some of the conductive structures individually in electrical communication with a memory cell of the vertical stack of memory cells and comprising a gate of an access device of the vertical stack of access devices. Related electronic systems and methods are also described.

In certain aspects, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view, one or more channel structures each extending through the core array region of the stack structure, and one or more contact structures each extending through the stack structure, wherein each of the one or more contact structures includes a head portion and a body portion, and a width of the head portion of the respective contact structure is larger than that of the body portion of the respective contact structure.

A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

A semiconductor device includes a wiring layer; a first stacked body disposed on the wiring layer; a second stacked body disposed on the first stacked body in a stacking direction; and a first resin body disposed around a periphery of the first stacked body. The first stacked body includes a first pad electrically connected to the wiring layer, a first device layer electrically connected to the first pad, and a first electrode electrically connected to the first device layer. The second stacked body includes a second pad electrically connected to the first electrode and a second device layer electrically connected to the second pad. In the stacking direction, the first resin body is vertically located closer to the wiring layer than an interface between the first stacked body and the second stacked body.

A structure includes a first metal structure including a first upper metal feature having a first sidewall spacer thereabout, and a first lower metal feature under the first upper metal feature. The first lower metal feature includes a sidewall devoid of the first sidewall spacer. The structure also includes a second metal structure spaced from the first metal structure. The second metal structure includes a second upper metal feature having a second sidewall spacer thereabout, and a second lower metal feature under the first upper metal feature. The second lower metal feature includes a sidewall devoid of the second sidewall spacer. A dielectric is between the first metal structure and the second metal structure. The dielectric is devoid of any voids therein, and the opening it fills has a high aspect ratio. A related method is also provided.

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.